Training Module: Altera Cyclone II FPGA

Introduction

• Overview of Cyclone II family FPGA
• Definition of programmable logic
  • Configurable logic with programmable interconnections
  • Memory cells define logic functions and interconnections

FPGA Applications

• Random logic, device controllers, communication encoding, filtering
• Prototyping designs for gate arrays
• Custom computing machines (executing software on programmable parts)

Altera's Approach

• Complements CPLDs and FPGAs with:
  • Sophisticated software tools
  • Pre-verified, configurable IP cores
  • Software core processor (Nios II)
  • Development kits and reference designs
• Benefits: Faster design process, faster time to market, lower development costs

Cyclone II Family Benefits

• Extension of low-cost FPGA density range to 68,416 logic elements
• Up to 622 usable I/O pins
• Up to 1.1 megabits of embedded memory
• Manufactured on 300mm wafers using TSMC's 90nm process
• High performance and low power consumption
• Supports complex digital systems on a single chip

Technical Features

1. Embedded Multipliers

   • Up to two 9x9-bit multipliers or one 18x18-bit multiplier
   • Up to 250 MHz performance

2. External Memory Interfaces

   • SDR SDRAM, DDR SDRAM, DDR2 SDRAM, QDR2 SRAM
   • Clock speeds up to 167 MHz for DDR and DDR2
   • Clock speeds up to 160 MHz for QDR2

3. Phase-Locked Loops (PLLs)

   • Up to 4 PLLs per device
   • Advanced features: clock switchover, multiplication, division, phase shifting, programmable duty cycle

4. Vertical Migration

   • Migratable within the same package (e.g., EP2C35 to EP2C70)

5. Nios II Embedded Processor Support

   • Custom embedded processing solutions
   • Co-processing or replacing existing processors

6. Quartus II Design Software

   • Supports all Cyclone II devices
   • Integration with SOPC builder and DSP builder for embedded and DSP applications

Architecture

• Two-dimensional row and column-based architecture
• Signal interconnections between logic array blocks, memory blocks, and multipliers
• Logic Array Blocks (LABs) containing 16 logic elements (LEs)
  • Cyclone II devices range from 4608 to 68,416 LEs
  • LABs grouped into rows and columns

Interconnects and I/O Features

• High-speed backplane applications and high-end switch boxes
• Low Voltage Differential Signaling (LVDS)
  • Higher noise immunity, high-speed data rate transfers, low power consumption
  • Programmable drive strength control for various I/O standards

PCI Express and Hot Socketing

• PCI Express: High performance, flexibility, scalability, and software compatibility
• Hot Socketing: Insert/remove board during operation without affecting the system

I/O Banks and VREF Pins

• Separate power buses for each I/O bank
• Devices support varying numbers of I/O banks and VREF pins (e.g., EP2C5 devices - 4 I/O banks, EP2C70 devices - 8 I/O banks)

Clock Management with PLLs

• Zero delay buffer, jitter attenuator, low skew fan-out buffer, frequency synthesizer
• Four supported clock feedback modes: Normal, zero delay buffer, no compensation, source synchronous

Configuration

• Active serial configuration using low-cost serial devices with non-volatile memory
  • Simple 4-pin interface, small form factor

Ideal Applications

• Automotive, consumer, communications, video processing, test and measurement
• Optimized for low-cost applications with a comprehensive feature set