this is a training module for the altera cyclone to fpga welcome to this module on the cyclone tube family fpga from altera the module overviews the major features of the cyclone 2 family fpga programmable logic is loosely defined as a device with configurable logic and flip-flops linked together with programmable resources that control the interconnections user programmable memory cells control and define the function that the logic performs and how the various logic functions are interconnected thus a wide range of sequential circuits can be implemented on a low-cost pld though various devices use different architectures all are based on this fundamental idea fpgas have gained rapid acceptance over the past decade because users can apply them to a wide range of applications random logic integrating multiple splds device controllers communication encoding and filtering small to medium-sized systems with sram blocks and many more another interesting fpga application is prototyping designs to be implemented in gate arrays by using one or more large fpgas an application only beginning development is use of fpgas as custom computing machines this involves using the programmable parts to execute software rather than compiling the software for execution on a regular cpu altera understands programmable devices are part of a bigger picture and that true design success requires an array of other tools to that end altera complements the complex programmable logic devices cplds and field programmable gate arrays fpgas with sophisticated software tools pre-verified and configurable intellectual property ip cores a software core processor nios 2 development kits and reference designs our comprehensive solution portfolios result in a faster simplified design process and in turn faster time to market and lower development costs with altera solutions you can undertake your design confident that you will be able to meet your unique application design goals following the immensely successful first generation cyclone device family altera cyclone 2 fpgas extend the low-cost fpga density range to 68 416 logic elements and provide up to 622 usable i o pins and up to 1.1 megabits of embedded memory cyclone 2 fpgas are manufactured on 300 millimeter wafers using tsmc's 90 nanometer process to ensure rapid availability and low cost by minimizing silicon area cyclone 2 devices can support complex digital systems on a single chip at a cost that rivals that of a6 altera's low-cost fpgas cyclone 2 fpgas offer high performance and the low power consumption altera cyclone 2 fpgas extend the low-cost fpga density range to 68 416 logic elements and provide up to 622 usable i o pins and up to 1.1 megabits of embedded memory embedded multiplier block can implement up to either two nine by nine bit multipliers or one 18 by 18 bit multiplier with up to 250 mhz performance embedded multipliers are arranged in columns across the device cyclone 2 devices support a broad range of external memory interfaces such as sdr sdr ram ddr sdram ddr2 sdram and qdr2 sram dedicated clock delay control circuitry allows cyclone 2 devices to interface with an external memory device at clock speeds up to 167 megahertz or 333 megabits per second for ddr and ddr2 sd ram devices and 160 megahertz or 667 megabits per second for qdr2 sram devices each cyclone 2 device has up to 4 plls supporting advanced capabilities such as clock switchover and programmable switch over these plls offer clock multiplication and division phase shifting and programmable duty cycle and can be used to minimize clock delay and clock skew and to reduce or adjust clock to out and set up times altera cyclone 2 fpgas extend the low cost fpga density range to 68 416 logic elements and provide up to 622 usable i o pins and up to 1.1 megabits of embedded memory cyclone 2 devices include a powerful fpga feature set optimized for low-cost applications including a wide range of density memory embedded multiplier and packaging options cyclone 2 devices support a wide range of common external memory interfaces and i o protocols required in low-cost applications vertical migration means that you can migrate to devices whose dedicated pins configuration pins and power pins are the same for a given package across device densities cyclone 2 devices support vertical migration within the same package for example you can migrate between the ep2 c35 epc50 and ep2 c70 devices in the 672 pin fine line bga package cyclone 2 devices support the nys2 embedded processor which allows to implement custom fit embedded processing solutions cyclone 2 devices can also expand the peripheral set memory i o or performance of embedded processors single or multiple nios ii embedded processors can be designed into a cyclone 2 device to provide additional co-processing power or even replace existing embedded processors in your system using cyclone 2 and 9s2 together allow for the low-cost high-performance embedded processing solutions which allow you to extend your product's life cycle and improve time to market over standard product solutions nios and is2 are the soft process ip solutions for altera for embedded applications the table demonstrates the resource utilization or logic element usage summary for nios and is2 embedded processor with cyclone 2 fpgas nios 2 processor adds the advantage in better performance with with less silicone utilization and comparatively low cost altera's quartus ii design software supports all cyclone 2 family devices quartus 2 software has full integrity with advanced tools such as sopc builder and dsp builder for embedded and dsp applications respectively cyclone 2 devices contain a two-dimensional row and column-based architecture to implement custom logic column and row interconnects of varying speeds provide signal interconnections between logic array blocks embedded memory blocks and embedded multipliers the logic array consists of labs with 16 logic elements in each led an le is a small unit of logic providing efficient implementation of user logic functions labs are grouped into rows and columns across the device cyclone tuned devices range in density from 4608 to 68 416 les each lab consists of 16 less lab control signals le carrier chains registry chains and local interconnect from high-speed backplane applications to high-end switch boxes low voltage differential signaling lvds is the technology of choice lvds is a low voltage differential signaling standard allowing higher noise immunity than single-ended i o technologies its low voltage swing allows for high speed data rate transfers low power consumption and reduced electromagnetic interference cyclone 2 device ioes contain a bi-directional i o buffer and three registers for complete embedded bi-directional signal data rate transfer the ioe contains one input register one output register and one output enable register you can use the input registers for fast setup times and output registers for fast clock to output times additionally you can use the output enable register for fast clock to output enable timing the ioes are located in i o blocks around the periphery of the cyclone 2 device there are up to five ioes per block and i o block and up to 4 ioes per column i o block the row i o blocks drive row column or direct link interconnects the column i o blocks drive column interconnects the output buffer for each cyclone 2 device i o pin has a programmable drive strength control for certain i o standards the lv ttl lvcmos sstl-2 class 1 and 2 sstl-18 class 1 and 2 hstl-18 class 1 and 2 and hstl dash 1.5 class 1 and 2 standards have several levels of drive strength that you can control using minimum settings provided signal slew rate control to reduce system noise and signal overshoot the table shows the possible settings for the i o standards with drive strength control pci express is rapidly establishing itself as the successor to pci it provides high performance increased flexibility and scalability for next generation systems without increasing costs all while maintaining software compatibility with existing pci applications now you can easily design high volume low cost pci express solutions today with cyclone 2 fpga ep2 c15 or larger cyclone 2 devices offer hot socketing also known as hot plug-in hot insertion or hot swap and power sequencing support without the use of any external devices you can insert or remove a cyclone 2 board in a system during system operation without causing undesirable effects to the board or to the running system bus the hot socketing feature lessens the board design difficulty when using cyclone 2 devices on print circuit boards that also contain a mixture of 3.3 2.5 1.8 and 1.5 volt devices with the cyclone 2 hot socketing feature you no longer need to ensure a proper power up sequence for each device on the board the i o pins on the cyclone 2 device are grouped together into i o banks and each bank has a separate power bus ep2c5 and ep2c8 devices have four i o banks while ep2 c20 and ep2 c70 devices have eight i o banks each device io pin is associated with one i o bank to accommodate voltage reference i o standards each cycle into i o bank has a v reference bus each bank in ep2 c5 ep2c8 ep2c15 ep2c20 ep2c35 and epc 50 devices support two vref pins and each bank of ep2 c70 supports four vref pins cyclone 2 devices have up to four phase lock loops plls that provide robust clock management and synthesis for device clock management external system clock management and io interfaces cyclone 2 plls are versatile and can be used as a zero delay buffer a jitter attenuator a low skew fan out buffer or a frequency synthesizer cyclone 2 plls support 4 clock feedback modes normal mode zero delay buffer mode no compensation mode and source synchronous mode cyclone 2 pivot plls do not have support for external feedback mode all the supported clock feedback modes allow for multiplication and division phase shifting and programmable duty cycle in the active serial configuration scheme cyclone 2 devices are configured using a serial configuration device these configuration devices are low-cost devices with non-volatile memory that feature a simple 4-pin interface and a small form factor these features make serial configuration devices an ideal low-cost configuration solution this table shows the approximate uncompressed configuration file sizes for cyclone 2 devices to calculate the amount of storage space required for multiple device configurations add the file size of each device together cyclone 2 devices include a powerful fpga feature set optimized for low-cost applications including a wide range of density memory embedded multiplier and packaging options the low-cost and optimized feature set of the cyclone 2 fpgas make them ideal solutions for a wide array of automotive consumer communications video processing test and measurement and other end market solutions you