Basics of UVM (Universal Verification Methodology)

Jul 13, 2024

Basics of UVM (Universal Verification Methodology)

What is UVM?

  • UVM stands for Universal Verification Methodology.
  • It is a SystemVerilog language-based verification methodology.
  • Widely used across the VLSI industry.
  • Defined to build test benches for verifying design.

Advantages of UVM

  • Reuse of test bench components.
  • Development of Verification IP.
  • Easier migration from simulation to emulation environment.
  • Sequence-based stimulus generation.
  • Factory mechanisms for object creation and management.

UVM Testbench Architecture

High-Level Components

  • Test: Configures the test bench and starts the sequence.
  • Environment: A container for higher-level components like Agent and Scoreboard.
  • Scoreboard: Receives data items from Monitor and compares them with expected values.

Key Components of Agent

  • UVM Agent: Groups components specific to an interface or protocol.
    • Driver: Receives stimulus from Generator and drives packet-level data to DUT (Device Under Test).
    • Monitor: Observes pin-level activity and converts it into packet-level data sent to Scoreboard.
    • Sequencer: Routes data packets to/from the driver.
    • Sequence Item: Defines pin-level activity.

Component Processes

  • Test.svh: Includes all class definitions, UVM packages, and macros.
    • Contains clock generation logic and virtual interface.
  • Test.sv: Configures environment and stimulus.
    • Build Phase: Constructs environment.
    • Run Phase: Starts sequence.
  • Agent.svh: Instantiates components like Driver, Sequencer, and Monitor.
    • Build Phase: Constructs sub-components and connects interfaces.
  • Sequencer.svh: Routes sequence items to the driver.
    • Build Phase: Initializes sequencer.
  • Driver.svh: Drives data from sequencer to DUT.
    • Run Phase: Manages handshake and data items.
  • Monitor.svh: Writes transactions to analysis port when detected.
    • Run Phase: Constructs transaction objects and taps interface signals.
  • Config.svh (if needed): Custom configurations.

Conclusion

  • Summarized the basics and architecture of UVM.
  • Key advantages and components of UVM testbenches.

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