hello and welcome to semiconductor club here we talk about semiconductor engineering please show a thumbs up and subscribe to our channel in today's topic we will learn about basic of uvm advantages of uvm and uvm test bench architecture now on to the first sub-topic what is a uvm universal verification methodology uvm is a system verilog language based verification methodology which is widely used across vlsi industry uvm is a methodology defined to build test benches for verifying the design now on to the next subtopic advantages of uvm reuse of test bench components development of verification ip easier migration from simulation to emulation environment sequence based stimulus generation factory mechanisms and now on to the final part uvm testbench architecture test configuring the test bench initiate the test bench component construction process by building the next level down in the hierarchy example environment nth initiate the stimulus by starting the sequence environment it is a container component for grouping higher level components like agent and scoreboard scoreboard receive data items from monitor and compare them with expected value agent uvm agent groups the underscore component specific to an interface or protocol sequence item it defines the pin level activity generated by agent to drive to duty through the driver monitor observe the pin level activity on interface signal and converts into packet level which is sent to components such as scoreboard driver it received the stimulus from generator and drive the packet level data inside the transaction into pin level to dut sequence it defines the sequence in which the data items need to be generated and sent received to from the driver sequencer it is responsible for routing the data packets sequence underscore item generated in sequence to the driver or vice verse generator generates different input stimulus to be driven to out interface contains design signals that can be driven or monitored basic structure of uvm one testbench.svh testbench.s is module that creates an object of test class passes on interface pointer and start simulation using run underscore testo call include all class definition uvm packages and macros clock generation logic instantiate interface and pass to test top as virtual interface run test 2. test svh instantiate environment eeny config and stimulus build phase construct enven config get virtual interface handle from tb and pass it to nth run phase construct sequence start test pass sequence sector sequence sqr phase objection sec start sqr drop objection 3 and svh instantiate agent build phase pass virtual interface handle to agent after getting it from test add connect phase if scoreboard is present four sequence dot svh parameterize to type sequence item sec underscore item taskbody once sequence started it gets executed instantiate sec underscore item construct sec underscore item start underscore item sec underscore item randomize finish underscore item sec underscore item 5 sec underscore item dot svh declare all transaction variables implement do underscore copy convert to string functions six agent.svh instantiate all components to be present in agent like driver sequencer and monitor build phase construct all sub-components instantiated above get virtual interface from end and pass it to all the sub-components connect phase connect driver and sequence support to export seven sequencer dot svh parameterize to type sec underscore item build phase get virtual interface from agent 8. driver.svh build phase get virtual interface from agent parent or config database run phase forever begin get underscore next underscore item get sec underscore item from sequencer item underscore done handshake done from driver to sequencer end other apis like peak try underscore get put could also be used 9. monitor.svh analysis port monitor writes transaction objects to this port once get detected at the interface construct analysis port build phase get virtual interface handle from agent parent or config database run phase code functionality construct transaction objects sec underscore items tap signal at the interface through modport write transactions to analysis port 10 config.svh if needed and that was it for today hope you enjoyed this topic stay connected for the next lessons thanks for watching