Introduction to System Verilog UVM Register Abstraction

Overview

• Focus on the introductory part of System Verilog's UVM Register Abstraction Layer (RAL).
• Recap of previous topics related to RAL, including:
  • Introduction to UVM RAL
  • Front Door vs. Back Door methods
  • Types of predictions (auto, passive, and explicit)
  • Memory and register class definitions
  • Register database structure

Key Concepts

Register Database

• Each register has a desired value (what is intended) and a mirrored value (current state).
• Memory does not have desired and mirrored values.
• Update of desired and measured values occurs at the front door access.

Base Classes in RAL

• Register and memory definitions using UVM classes.
• Register models must extend from uvm_register.
• Use of uvm_reg_field to define fields in a register.
• Optional use of uvm_reg_file.

UVM Bridge Block

• Acts as a register block that contains a map of registers and memories.
• The map holds the offset address of each register/memory and pointers to adapters and sequencers.

Verification of DUT with a Single Register

Minimum Requirements for Test Bench Architecture

1. DUT must have at least one register or memory.
2. Register must have at least one field.
3. Register must have an address map.

Test Bench Architecture Overview

• DUT consists of a single register.
• Key components include:
  • Agent - interfaces with the DUT.
  • Sequencer - generates sequences of transactions.
  • Driver - drives signals into the DUT.
• Register model includes desired and mirrored values and a register map.

Example Code Walkthrough

DUT Definition

• Example DUT with a single register:
  • Input/output variables defined (logic type: clock, reset, address, write enable).
  • Write enable controls writing data to the DUT.
  • Internal register temp_reg defined.

Register Class Definition

• Extend from uvm_register:
  • Register class must be factory registered with UVM.
  • Define fields using uvm_reg_field.
  • Constructor requires width and coverage settings.

Configure Method

• Method has nine arguments for defining field properties:
  • Parent, size, LSB position, access type, volatility, reset value, reset capability, individual accessibility.
  • Mnemonic to remember: PSL AVR High.

Register Block Definition

• Extend from uvm_reg_block:
  • Create instances of registers, define base address, and size of the register.
  • Use methods to add registers to the map and lock the model to prevent further changes.

Future Videos

• Next video will cover:
  • Complete example including adapter, sequencer, driver.
  • Methods for handling register values (set, get, predict, update, read, write).
• Links to previous videos for additional context and code examples.

Conclusion

• The video provides a basic understanding of the Register Abstraction Layer in UVM.
• Encouraged practice by defining multiple registers within the DUT for better understanding.