Hello and welcome. In this video I will be talking about some introductory part to system verilog version of uvm brand register abstraction. Already we covered some topics in last few videos. related to this rail and the covered topics i have highlighted here okay so we discussed the introduction to basic introduction to uvm brand what rail is all about then we discuss what is a front door method and back door method which is faster and why we discussed that then we already had a discussion about the types of prediction auto prediction which is also referred as implicit prediction then passive prediction and the explicit prediction then we discussed how we can define the memory class as well as the register class with respect to drive as a part of a record then we also discuss the register database in that video we will we discussed that if our dut has some registers and memory in it how the database will be the register database will be so each register i will have a pair of a desired and mirrored value and for memory there is no any desired and mirror value so what is desired value what we think in the hardware register sorry what we want in the hardware register next this is what desired value or you can consider the value of the register for a next transaction what is mirror value it is like what we think in the hardware register now And we discussed this desired and measured value will updated by the predictor at each Front door right and right axis. Then we discussed some base classes Related to REL.
If we are defining register then how we can access that How we can define that register by extending it from UVAverage class then For that we have to define some fields then how we can define fields using uvm reg field Then we discussed this uvm reg file which is the optional one if you want we can add or we can you know remove it Then we discussed the memory base class if we if if our dut has memory in it how we can define a memory as a part of a then the register map and the last one is uvm bridge block so what this uvm bridge block it is nothing but a register below and it will it will con it will consist of a map so this map will have the offset address of all registers and memories in addition to offset address and you know of register in memory will have the pointer for adapter and sequencer in. Now here in this video I will just walk you through a concept that if our DUT has a single register in it how we can verify that using this register abstraction by considering a front door and in the later part we'll try to understand the backdoor access to so some basics for rel you know minimum requirements for including rel in our test bench there are some minimum requirements that should be there then only we can add this register abstraction layer in our test bench what are those so first requirement is at least our duty has a single register or memory in it. if our dvt has a register as it is defined over here then it should have at least a single field and the register should have an address map so these are the three minimum requirements for including real register abstraction layer in our test bench architecture remember this it is important now let me just give you the overview the test bench architecture overview if you are adding the rail in our you know test bench architecture so this is what our dut we are considering it has single register and we are considering the front door for that we should have the agent it should have sequencer and driver so this driver can drive the stimulus to the dut through this interface and we have to define the register model so this register model will have the desired value and mirror value variables along with it should have register map so this register map will have the base address and the instance of a register let me just walk you through the code how we can define a register model for the DUT which has a single register in it.
So let's consider our DUT has a single register in it. So I have defined a DUT code over here as you can see on the screen that this you know DUT has a single register in it. So this module DUT and module DUT.
In this I have defined some input and output variables for that DUT. Those are logic type, clock, reset address and the write enable. So this write enable is one then we are writing the data inside the DUT.
If it is zero we are reading the data inside with the help of this output mode DUT. now as a part of this dts i told you that we are defining simple one register so logic 7 down to 0 temp reg 0 this is the internal register now the code is here the real logic for that is always block i'm using always underscore ff i'm using system very log version of hdl to define hard if reset is there then the register content will be zero else if the write enable is there and the address is zero then the input should be there input will apply you know you know adding inside this register restoring inside this register else if the write enable is zero we are just reading the content of this register on this dout port if address is very simple and just we are here defining the interface as a part of this dut interface and an interface in that i am defining all the input and output ports is a logical this is what a simple dut okay just we are commenting it out because we are not applying any stimulus to the dut Just we'll take a simple example that our a duty has one resistor in it how to define a resistor model for that Okay, so as a part of this video I'm not explaining you the adapter layer over here and the agent and all just will define a resistor class Then we'll define one register block in that how we can add this Register and how to create and configure I just walk you through as a part of this video. In the later video we will try to see the complete example with a code.
So tick include uvm macros dot svh and import uvm package colon colon install. These two lines are mandatory in order to get an access of uvm macros and all uvm processes. Then remember I told you that if we are defining our own register class then we have to extend it from uvm register.
so class register 0 which is extending from uvm bridge and remember as a part of register All the classes are the object classes. So we have to register them using fact object. It is factory registration method.
So for this rel or for this register class tick uobm object details and we are defining a single field for this register and we are defining it as a rand so that in future if we can randomize make use of random we can randomize this property for this field we can randomize so uvm reg field f0 is a field for this register single field we are considering because it is a minimum requirement for us that at least single field should be there for the register then as it is the object class its default constructor expecting one argument along with this one argument name we are providing two additional arguments over here so this 8 is a width for this you know register register field width of a register we are defining as a part of this constructor and we don't want any separate coverage for this register hence the third argument should be uvm no coverage then as it is an object class we cannot define phases over here so the executable logic we need to define inside of virtual function void build where we are defining one function build and inside that we are creating this field f0 which we have defined over here using factories create method so how to create f0 is equal to uvm bridge field type id create okay and as a part of this you know function build we have to define one configure method and this configure method will have some nine arguments in it so parent size lsb position type of access volatile in nature reset value has reset is ran and individual accessibility so these are the nine arguments so if you want to remember uh how we can remember this i have i have you know remember this like this psl avr high you can make your own technique to remember how i'm remembering i just walk you through that so this psl i'm considering partial you can take any one avr means arrive and hi hi and how i'm you know you making this how i am remembering this is like this simple technique and now we will map this psl avr high parcel arrive high okay so this psl means this dot parent dot size dot lsb position these three are then avr just i'm considering arrive so dot access dot volatile dot reset AVR then H double I high means has reset is ran and dot individual accessible you can make your own technical let me just walk you through all these you know arguments 9.0 dot parent is a current class hence in the parenthesis we have to give this so this will refer to this register R0 Then the size is nothing but the width we have to define which is 8 in our case. You can see over here also. Then the LSB position for this is 0. So if you see over here, this is what the right hand side is a LSB for. And this, sorry, this left hand side is a MSB. okay for this register so this is what the lsb position 0 we are considering the type of access it should have this read write access read only write only access so generally we are defining right read and write access so we will understand this access policy in the later videos we'll understand that but as of now just consider this field has both the access read and write then dot volatile if it is one means the field can't change between consecutive excesses dot reset is the reset value power on reset for this field is zero then has reset means the field support the reset or not so hence we are giving in the parenthesis is ran meaning the field is you know capable of accepting the randomized things so field can be randomized means when the parenthesis we are giving one meaning it this field support the random okay randomize method then dot individual accessible meaning this field whether it is individually accessible or not so in the parenthesis we have to provide one if we want this field to be individually accessible so this is what the nine arguments you can remember with this simple technique parcel arrived high psl avr you can make your own technique too okay so Remember as a part of simple test bench architecture only we have to define these things But let's consider our DUT is a bit complex.
It has Thousand one thousand number of you know registers then defining our own, you know methods This you know register and all it's a bit complex. So for that there is you know Automation is here. We will see that concept later so we are not defining the ip exit file is there that if you are just providing the information register information it will automatically tool will automatically generate the register model for us but for our understanding we are just considering a simple example how to define all the things now the register block which is a top one which is you know extending from uvm bridge block it is also an object class we have registered the tic uobm object it is factory registration then here we have to define the instance of this register register 0 register 0 h is an instance for this register r 0 okay sorry register 0 r 0 a register 0 h is an instance for this register 0 okay then as a part of this class we have to define the default construct as it is an object class its default constructor expecting one argument along with we have to define the second argument is uvm no coverage because we don't want any separate coverage for this register block now as a part of this register block we have to define one build method so virtual function build okay here we have to define as it is a void it is not returning anything we have to define it as a point then here we have to create the instance for this register we have to allocate a memory for this register instance using factories create method so register instance register name type id and create and we have to call the build method of this register so as you can see build it will this register instance dot build will call this Build method of this register, which has you know configure information for this field then we have to define the configure method for the instance of this is Register 0 H dot configure and this will refer to the current class So current class is register block here then here we have to define a create map okay so default map is equal to create map and in the parenthesis we have to provide four arguments so first is the instance default map then the second one is a base address third one is the size in byte so the field as you can see over here is of 8 bit right so 1 into 8 is equal to 8 right so that that's why we have to define the size one which is in byte and the fourth argument will be uvm little indian so what this little indian let me show you if you see the literature you will find that this you know create map we have to provide you know some arguments so four are mandatory the name the base address the size in byte and the indian so what is this indian means let me just show you so this indian means uh you know uvm Indianness underscore a type on the site is specifies the byte ordering So if you are defining UVM no Indian means byte ordering not be not applicable if you are defining UVM little Indian then least significant byte first in the Consecutive address then you can define UVM big Indian UVM little 5 for big 5 So mostly we are defining only uvm little Indian so least significant byte in first in the consecutive at least So the fourth argument will be uvm little Indian Then we have to add this register inside this map of so what is for that?
There is a method called add reg and inside this we have to provide three Arguments, okay, so you can see on on this screen in the parenthesis we have to define three arguments so first default map dot add reg inside this parenthesis these three arguments the instance of the register then the offset address so here offset address we are considering zero and the type of axis so generally we are defining here read and write axis so if you see the literature you will find this add reg method okay add reg and here you'll find it should have some arguments so mandatory one first three only instance the offset and the type of access then we have to define one lock model it is mandatory so what this lock model will do it will lock a model and it will then build the map it is mandatory right once the model it is logged we cannot change the structure of our register block meaning we cannot add the further memories and you know register inside this model okay so if you see the literature you will find some information related to this lock model so once we have to define we have to lock the model so this after locking the model it will build the address map okay and once the model is locked no further structure changes can be there should be there such as we cannot add the further at you know registers and memories inside a model and it is not possible to unlock the model once the model is locked okay and just end class register and just as a part of top class i am defining the module inside this module and module class i'm just defining the instance of a register block and within initial beginning block just allocating a memory for this register block and just calling the build method of this register block so right now we are not considering the adapter and the sequencer and all because we are not writing anything inside the duty just for getting a flow how we can define a register class and how we can define a registered block we have just wrote those code only in the next video we will uh you know add all those things adapter you know sequencer driver and all and then we will try to understand more about this okay so if you just run this code if there is no any error syntax error and nothing is there you'll find the it will pass like meaning there is no any error and there is two warnings you can ignore this warning as a whole so this is what you know simply we can define a register model and you know we can define a register in our dut okay in the next video uh we will try to you know explore more about as a part of this style how we can define adapter layer how we can write the you know values inside the dut register how we can get the desired and mirrored value what are different methods like set get mirrored value, the predict method, update method, write method, read method all the things we will try to understand from the later videos I will put a link of those videos which I covered as a part of RHEL earlier so that you can go through those videos and if you are proceeding after those videos you will find this concept easy to understand I'll put a link of this video inside the description you can play around with those code. So what you can do you can define two resistors in our DoD and as a part of that you can define a resistor Classes to register classes you can configure them and you can you know create those classes here inside a register model And you can play around with those code so that you will have the clear picture and clear understand Okay, so with this I hope you have understood a basic of resistor abstraction layer and also i hope you understood that how we can define a resistor inside our rel in our inside our test bench architecture how we can define a resistor block how we can add the resistor instance how we can configure how we can define a map and we can add this resistor inside the map and also i hope you enjoyed this video so thanks for watching thank you