Sequential Circuit Testing Tutorial

Key Topics

• Testing sequential circuits
• Controllability and observability
• Scan cell design

Testing Internal Nodes

• Primary Inputs: Directly available inputs
  • Example: Inputs to an AND gate
• Internal Gates: Inputs not directly connected to primary inputs
  • Lacks controllability and observability
• Scan Cell Design: Used for testing internal gates

Scan Cell Structure

• Scan Cell Components: D flip flop, MUX
• Modes of Operation:
  1. Normal mode: Operates as usual
  2. Test mode: Tests the circuit

Components Explained

• MUX: Selects between normal input and scan input
• D Flip Flop: Stores the output
• Scan Enable Signal: Determines mode (test or normal)

Functioning of Scan Cells

• Cascade Connection: Scan cells connected in series
• Scan Mode:
  • Set Scan Enable to 1
  • Inputs shift across flip-flops on clock cycles
• Normal Mode:
  • Set Scan Enable to 0
  • Circuit operates normally, captures results in flip-flops

Example Process

1. Scan Mode:
   • Apply scan inputs (e.g., 1, 0, 1)
   • Shift inputs through flip-flops
2. Normal Mode:
   • Set Scan Enable to 0
   • Apply primary inputs
   • Capture outputs in scan cells
3. Shift Out Results:
   • Apply clock with Scan Enable set to 1
   • Shift captured outputs to scan out

Testing Process

• Use scan cells to control and observe internal gate outputs
• Apply clock cycles to shift inputs and capture outputs
• Verify whether outputs match expected results

Simulation Results

• Example sequence of scan inputs and clock cycles
• Verify whether internal gates produce correct results
• Identify faults

Conversion to Scan Cell Design

• Replace D flip flops with scan cells
• Ensure proper functionality in both modes (shift register for test, normal circuit otherwise)

Practical Tips

• Identify flip flop locations
• Ensure cascade connection is correct
• Test output using scan output (S0)

Conclusion

• Scan cell design crucial for testing hardware faults
• Effective for controlling and observing internal nodes
• For more detailed tutorials and Verilog code: verilogcode.blogspot.team