hello guys this is a small tutorial about testing of sequential circuits wherein you have a lot of problems like the testing of internal nodes if you can see the screen here i have a rtl of some random circuit where i have some primary inputs because you can see the mouse these are the primary inputs which are available but primary inputs i mean the inputs which are directly available to me when i can give the inputs for example this one this but this present input this one this one and this this all these are primary inputs by which i can give the test test inputs let's consider design gate for example now the inputs if i want to test this particular and gate all i need to do is to just give this input which is directly the primary input give this input which is again the primary input and then i can directly give the input to this particular gate if you consider this and gate now for example this is also connected directly to the parameter inputs this one and this one so i can directly give the inputs to this gate 2. now let's consider this and gate now the third one here as you can see i don't the input to this gate that is this input and this input they are not directly connected to the primary inputs so it means i don't have any controllability on this particular gate i can't have any control on this gate and it is internal to the design and i cannot even observe the output of this particular gate so i can say the observability is zero so in such a case where i have a design where i want to test a gate or any logic which is present within the within the circuits which is internal and which cannot be controlled by the primary inputs then we go for scan cell design let's take this particular scan cell how it is designed a scan cell is nothing but a simple d flip flop which has been modified to operate in two types of mode for example let me double click this scan cell and double click it now you can see that within this cancel there is a mux and as usual the d flip flops i just added a mux in front of a d flip flop and this d flip flop has the input a clock which is directly from the main clock as you can see and the output from the mux and this mux has two inputs one directly coming from the ion gate and another coming from input called as the scan input which is here the scan input now there is in order to select either the input from the ion gate or the input from the scan input which is which is one of the primary inputs now there is a select line this is select line as you can see this select line when it is one it will take the inputs from the scan enable that is the scan input and when it is zero it will take the input from the normal angle so when we make scan enable signal is equal to one when you make the scannable signal going let me just zoom it out for you yeah here is the scan enable signal when i make this one the circuit is now said to be in a test mode it means i want to test the circuit now what i'm exactly trying to do is when the scan enable is one the input er from scan input it goes here and it goes here and it goes comes out from the output of the dp what i have done is i just made a cascade connection between all the d flip flops if i'll just remove i'll just zoom it out okay as you can as you can see the output of this cancel is connected to you can see the output of this is connected to the input of this input of this that is the scan input of this and the output of this is been connected to scan input of this so and the output of this is connected to input of the and gate just if you notice it clearly let me zoom it out the output of this flip flop second flip flop is counted a third the output of third is connected to the input of the ion gate which i want to test now let's see output of the first cancel it is connected to the first input of my and gate and output of my thirds cancel is connected to the second input of the ion gate now because this cell this cell and this cell are connected in cascade and they can they are connected in cascade only when i make the scan enable signal this one is equal to one when i make this one it becomes a simple scan cell where the inputs which are given here they get shifted one by one for every clock for example if i make if they make the scan enable one they are in cascade now the output of this is going to output of this output of this goes towards this an output of this get applied to input of this right now i apply a scan input let's say 1 i apply scan input signal 1 and make scan enable is equal to one which means it is in the cascade mode the scan mode and one immediately when i apply a clock cycle one clock cycle what happens the scan input of this comes here the output of this comes as output of this indirectly when the flip flops are in cascade they act like a shift resistor i apply one here and apply on clock that one appears output here now next let's say i applied zero here and applied one more clock the one which was present here comes as the output of the second scan cell and zero comes as output of the first cancer now let's apply one more one here and apply one more clock the one which is present here comes now comes as output of the third scan cell and output of this comes as output of the second scan cell and the input appears as the output of the first scan cell so that just shifted now after uh shifted if you can just see after three clock cycle and three test inputs you are actually given the input to this iron gate let's say that i have given one zero one again one zero one and applied three clock cycles the one will be appeared will be here at the output of the first cancel which is also the input to this and gate so i applied indirectly one to this and gate and output of this scan cell that is this is 1 now which is nothing but input of the input of the and gate which is the second input so indirectly i apply two inputs to indicate and that is what i wanted i did not have any control to give inputs to this particular and gate i know by using the scan cells and making scan enable 1 giving the scan inputs and applying three clock cycle i have set up my and gate input two one here and one so what do you expect the output of the and gate to be now it has to be one right it has to be one now uh if i make scanning let's say the output of this is one up but it will not be captured capture in the sense it will not be stored in this cancel because the scan enable is still one now let's say now i have made scan analysis zero now the circuit will operate in its normal mode it means it is not not anymore a test circuit it is a circuit for which it was designed make scan enable is equal to zero give the primary inputs whatever you need give a1 e2 right and here you a3 e4 what happens when you make scanning bullet is equal to zero it will operate it will operate in the normal mode and this ion it will also operate with the test inputs which you had given you had given one one now that one one has given the output one if this is not faulty it will give some other output if it is 40 it's fault free now i just want to see whether for given one and one to this input whether it has given one how i can do this now yeah whatever made your mate scan enable is equal to zero the test the primary inputs have been applied now after making scanning to zero after applying the primary inputs now apply one clock cycle what happens the in the output of the combinational gate that is output of this gate get captured in the scan cell output of this and gets captured captured in this cancel output of this and gets and get get captured this cancer correct now i make scan enable 0 and apply 1 clock indirectly or captured the output response of this i indicate which was under consideration now in the scan cell number two it is captured now i want to see if you want to see this output is one or zero directly you can take the output from q but q is the output of the circuit we have made a provision to see the scanned input and scanned output by giving another output called as scan out here now if i apply one more clock cycle and make scan enable is equal to one what happens when i make scan enable is equal to one one second they will act like shift resistors the output of x1 will come to output of x2 output of x2 will come as output x3 right so if i apply one more clock cycle after scannable one the captured the captured response of iron gate at x2 will appear at output of output of x3 and which is available at s0 if this one this output is 1 now it means my and gate this and gate is fault free if it is 0 i can say this one is failed so this is how we can test any internal circuits any internal gates with the help of scans let us have a look at the simulation result uh here i have written the code for this particular particular configuration and made the test modes let's go and check okay okay here is the simulation i've written the test pins for that just run this okay wait for the results okay just increase the time run okay here's the setup okay okay here we go you can see this is my first clock rising edge in the first rising edge what is my scan my homemade scan enable is equal to one as you can see i have given the first scan input as one second clock cycle the scan enable is one scan input is zero it means my second scan input is zero third clock cycle scan enable is one scan input is one it means after three o'clock cycles i have actually i've actually given one zero one to the present at the output of my scan cell one scan cell 2 and scan file 3. indirectly i have set the output input of the i first and gate 2d 1 and second input also to be 1 that is what i require that's why i shifted 1 zero and one so that the first and the last becomes one and one and one get applied to my and gate let's go again back to the simulation okay so after this first clock cycle second clock cycle third clock cycle i have made scan enable is equal to zero here you can see the scan enable is zero now it means now the responses are captured because rtl it means the output of this gets captured here output of this and gets get captured the output of this and gate gets captured here now after making scanner one i have played one more clock right one more clock but skill the stan enable is zero it means i'm capturing the response here again what i made i made scan enable is one making it once again a shift resistor and applied one more clock after this clock we expect we want to expect the response which is captured in x2 that is nothing but the response of in2 will appear at the output of x3 which is available at s0 let's see whether it is 0 we have one or zero at s zero here you can see it is one it means my ion gate is working perfectly this is how we can test any a circuit in general and we can test the internal gates whether they are properly functioning or not scancel is mainly used to test for hardware faults like a circuit open or a circuit close if you want still interested in going about experimenting this you can take the test bench circuits like the issc s 2 7 which i used here my acc and i written little let us go to the ideal of this as a more complex design which is available which are also called as the test and circuits and let's run the my idea is to just show you how big can a sequential circuit be and how to convert that design to a scan cell design okay my article is ready okay fine finally here you can see it's a bigger circuit now wherever i find d flip flop i have to just replace it by scan cell see here there was a d flip flop see this is the flip flop i replaced it with my scan cell here is a also there was a d flip flop i replaced it by my scan cell and this is how you can convert any circuits from a normal circuit to a test circuit you have to just identify where are the d flip flop present in your design and then replace the d flip curve with your scan cell the main thing which you have to do is to properly make sure that when scan enable is one the scan cells are in cascade they must act like shift resistors and when scan enable is zero you must not alter the design of your circuit and that was a short tutorial about scan cell design for more details you can log on to my blog verilog code dot blogspot dot team