Static Timing Analysis - CMOS Basics

CMOS Inverter Basics

Previous Lecture: CMOS modeling and inverter characteristics
This Lecture: Charging and discharging of output, waveforms, propagation delay, slew
CMOS Inverter: Basic logic implementation
- Input 0: PMOS on, NMOS off -> Low resistance path from PMOS charges output (Q) to logic high (1)
- Input 1: PMOS off, NMOS on -> Low resistance path allows load to discharge to ground (logic low, 0)
- Waveform:
  - Ideal: Instantaneous change from 0 to 1 and 1 to 0
  - Real Life: Takes time to transition

Graphical Representation:
- Charging Waveform: Exponential rise to VDD
- Discharging Waveform: Exponential decay to 0
Mathematical Equations:
- Charging:
  - Output Voltage, Vo = VDD (1 - e^(-t/RC))
  - C = Capacitive load
  - RDH = Drive high resistance of PMOS
- Discharging:
  - Output Voltage, Vo = VDD e^(-t/RC)
  - C = Capacitive load
  - RDL = Drive low resistance (NMOS)

Definition: Time taken for a cell (e.g., buffer) to transfer data from input to output
Example: Buffer B transfers data from input A to output Z
Waveforms:
- Input A: Logic 0 to 1 rise
- Output Z: Same as A but delayed
- Rise Time:
  - TRA = Rise time of A
  - TRZ = Rise time of Z
  - Propagation delay (ΔTP) = 50% of (TRZ - TRA)
- Fall Time:
  - TFA = Fall time of A
  - TFZ = Fall time of Z
  - Propagation delay (ΔTP) = 50% of (TFZ - TFA)