hello everyone welcome to vlsi academy this is fourth lecture on static timing analysis series and this is related to cmos basic concepts in previous video we understood about cmos modeling and saw the working of cmos inverter and its characteristics now we will look into cmos charging and discharging of output and waveforms propagation delay and slew of waveforms we already know that cmos inverter is the most basic kind of logic implementation of cmos and what happens is when we provide input as 0 at that time the upper transistor which is a pmos it turns on and the lower transistor which is an nmos it turns off when the logic is 0 at the input and hence it will provide a low resistance path from pmos and q will charge so whatever the previous state is it will go to logic high so that will be logic 1 and it if there's a capacitive load here it will charge to logic high voltage and when we give a as one at that time this will turn off and the below transistor will turn on and it will provide a low resistance path for the load and hence this load will discharge to the ground and hence this logic one will turn to zero if we see the waveform of the output it will look something like this so this q will actually go from 0 to 1 when it is charged and it goes from 1 to 0 when it is discharged but this is ideal case and in real life it doesn't happen like this output does not charge or discharge instantaneously in real time output takes some time to go to logic 1 or logic 0. the charging or discharging of the output can be shown graphically like this this is the charging waveform this is discharging waveform this is the real case scenario the mathematical equation for implementation of charging of load is this here output voltage vo is vdd into 1 minus e raised to power minus t by rc dth so c here is capacitive load which we have represented by this capacitor rdh is the resistance of the transistor here rdh represents the drive high resistance of pmos because it pulls the output load to logic high irrespective of previous value this is mathematical equation of discharging of load where c is again the capacitive load and rdl means drive low resistance of cmos since the nmos pulls down the output to logic low this is called as drive low resistance now let's try to understand these mathematical equations graphically so let's say on x axis we have time here and we are trying to plot with respect to output voltage now when initially time is 0 so t will be 0 so e raised to the power of 0 that will be 1 1 minus 1 is 0 when time is 0 at that time your output voltage will also be zero now as time keep on increasing what will happen is your t will increase when t increases this net value e raised to the power minus t by rc this will decrease but since we are subtracting it from 1 so 1 minus this will actually increase so net value will be increasing so output voltage will keep on increasing with respect to time since it is exponential so you will see the growth also as exponential it will be something like this and what happens is at the time of t as infinity that is a very high value what will happen is this will come to very small value and hence this net value is very small so 1 minus very small value will actually be equivalent to somewhere around 1 only that means output voltage will reach to vdd at the time of infinity similarly we can plot graph for discharging of waveform here t is on x axis y output on y axis now when initially t will be 0 at that time this e raised to the power 0 means v out will be equivalent to v dd so let's say your logic high is vdd so initially your output voltage will be at vdd that is logic one and as time keep on increasing this net value keep on decreasing and exponential decrease means when t is infinity at that time this will be a very small value and it will come down to zero that means output voltage will be zero at the time of infinity and since it is an exponential decay we can plot it like this this is how we plot the graph for charging or discharging of cmos now that we have understood the rising and falling waveforms of cmos logic now let us try to understand the meaning of propagation delay propagation delay typically refers to the time taken by the cell to transfer the data from input to output for example let's say there is a buffer and its input is a and output says z then the time taken by this buffer b to transfer the data from a to z is called as propagation delay of this buffer b let's try to understand further with the waveform so let's say waveform for a is something like this and since it is a buffer the output z will also be same as a but there is some delay so let's say the output waveform of z is like this in our example this is logic 0 this is 1 this is logic zero this is one and let's say we have a time frame reference t now rise time refers to go from zero to one so for waveform a the t r a is let's say the rise time and in z wave form time taken by waveform to go from 0 to 1 is let's say trz now typically 50 of the threshold is used for delay measurement for most of the standard cell libs so which means that 50 percent of your rise time is taken as the reference point here and 50 percent of your rise time will be taken as the reference point here to calculate the delay hence propagation delay let's say delta t p will be t r z minus t r a and the fifty percent of that value that will be 0.5 this is your rise time propagation delay similarly fall time refers to time taken by the waveform to go from 1 to 0 here and here also time taken by the waveform z to go from 1 to 0 so for waveform a let's say fall time is dfa and for waveform z let's say fall time is tf z as we told earlier that reference point for calculation of propagation delay will be 50 of the value here and 50 percent of the value here so propagation delay in case of fall waveform will be delta t p again will be 0.5 times of t f z minus t f a this is how we calculate the propagation delay and that's all for today going forward we will understand about slew of waveform what is q and other important concepts which are related to static timing analysis please do share about your feedback in the comment section please like share and subscribe to the channel and share it with anyone who is interested to learn about vlsi thank you