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ARM Based Development: Session 32 - AMBA Architecture

Jul 1, 2024

ARM Based Development

Session 32: AMBA Architecture

  • Focus: AMBA Architecture
  • Topics to be covered: Overview, AHB, APB buses, transactions, signals, and APB bridge.

Introduction to AMBA Architecture

  • AMBA: Advanced Microcontroller Bus Architecture, a de facto standard for on-chip communication.
    • ARM's specification for interconnect standard.
    • Motivation: facilitate integration of IP (IPs like cache controller, MMU, MPU, FPU, etc.) with low power and performance efficiency.
    • Market: Target for low-power devices (e.g., mobile, tablets, embedded devices).
    • Key feature: Enables uniform layer for connecting various components.
    • Open Standard: Initially for ARM, but now adopted widely.

Core Concepts

  • Bandwidth: Bytes per second over the bus.
  • Latency: Time taken for an address data cycle (memory to processor data transfer time).
  • Scalability: Number of devices connected and bus ownership arbitration.
  • Master-Slave: Multiple masters (e.g., ARM, DSP), centralized arbiter decides bus control.
  • Burst Transfer: Transfers starting from a specific address with subsequent addresses aligning sequentially.
  • Split Transaction: Interleaving transactions for efficient parallelism.
  • Low Power Design: Bus consuming minimal power during transactions and idle states.

Architectural Overview

  • SoC (System on Chip): Connection and management of functional blocks.
  • Testing: Features to test modules independently within SoC.
  • Design Reuse: Adaptation for IPs and compatibility with third-party products.
  • Variety of SoCs: Supports wide range from low-power devices to high-performance systems.
  • Standard Growth: Ecosystem and third-party support.

AMBA Bus Types

  • AHB (Advanced High-performance Bus): High performance, pipelined operation, multiple masters, burst and split transfers.
  • ASB (Advanced System Bus): Alternative to AHB for lower performance systems.
  • APB (Advanced Peripheral Bus): Low power, simple interface, used for connecting low performance peripherals.

Detailed Bus Analysis

Advanced High-performance Bus (AHB)

  • Pipelined Operation: Overlapping address and data phases for efficiency.
  • Connections: Multiple masters (e.g., processors), on-chip/off-chip memory interfaces.
  • Transaction Cycle: Address phase followed by data phase (Read/Write handled by HREADY signal).
  • Split Transactions: Allowing interleaving different master transactions.
  • Arbiter Role: Centralized control over bus requests and grants.
    • Master's Sequence: Request to Arbiter → Granted → Transaction execution.

Advanced Peripheral Bus (APB)

  • States: Idle, Setup, Enable.
  • Simple Operations: Less complexity, optimized for minimal power consumption.
  • Bridge: Connects APB to AHB/ASB for handling low-performance peripherals without impacting high-performance bus.
  • Transaction: Setup followed by Enable and sustaining selected signals until next transaction.

APB Bridge

  • Role: Acts as master on APB side and a slave on AHB side to buffer and manage transactions efficiently.
  • Function: Completes transactions without La-hazardous effects on high-performance AHB transactions.

Practical Example

  • Typical Microcontroller Example: Illustrates an SoC with both AHB and APB buses connected via APB bridge.
  • Master-Slave Setup in SoC: ARM processor, DMA, external memory interfaces.
    • AHB Master: ARM processor initiates transactions on AHB side.
    • APB Bridge: Manages low-performance peripheral transactions.

Bus Transfers and Signals

AHB Transactions

  • Protocol: Multi-master system without tri-state buffers within SoC.
  • Data Transfer: Pipelined address phase overlaps with previous data phase for efficiency.
  • Split Transactions: Idling for arbiter to manage bus handoffs between masters.
  • Bus Width: Recommended 32 bits to 256 bits, flexibility up to 1024 bits.

APB Transactions

  • APB State Transitions: Idle → Setup → Enable.
  • Read/Write Cycles: Data transfer and maintaining signal stability to save power.

Conclusion

  • AMBA Overview: Provides an interconnect standard for efficient SoC design.
  • Next Session: Focus on some peripheral modules.

Thank you and see you in the next lecture!

Full transcript