ARM Based Development: Session 32 - AMBA Architecture

Hello friends. So, welcome you all to the ARM Based Development course session 32. In this session we are going to be covering AMBA architecture ok. So, this is a different from whatever we have discussed so, far this is about the DAC interconnect ok. Let me nudge it. So, we will be covering some overview of what is AMBA architecture is all about and then I will show you a example structure of an AMBA architecture along with ARM processor in it and then we will go into the details of AHB and APB feature AAP APB bus and what are the transactions and signals. And then APB bridge also in some other modules and related to the AMBA architecture. So, before we come from to this discussion I would like to give you some overview ok. What is this specification and why it was designed by ARM? This is the interconnect standard from ARM ok. So, what was the motivation how does it help in our design of primary resources which is AMBA. So, let us look at that introduction part, AMBA is a an acronym of advanced microcontroller bus architecture it is the de facto standard for on chip communication. So, what is the de facto standard ? Suppose you have ARM core and then when ARM define this processor and then we have model business model versidue on at an high speed and then they also gave other IPs like cache controller right and then MMU MPU ok. These are all something which is these are all this this this modules are going to be is a SOP final SOP ok and then FPU. So, they define design different cache controller ok. So, this will in turn will be giving instruction and then data caches. So, the design all this modules at an IP. Now, having given this if there is no uniform layer connecting them all together ok then there will be an issue. Because the performance and power as well as cost everything that we gain using this modules ok will be actually only when we have an interconnect ok. With this well design and meets the requirements of the low power design that on its targeting that the that this is the low power IP chips and for the applications low power application where mobile applications or tablet and any other embedded low power devices. So, the target market is this kind of a environment ok this kind of a products. So, it is not enough if only this IPs are given, but there should be some standard interconnect also defined around with this IPs then it will be easier for people to buy this IPs and build their own IPs and interface with the customers items or modules in the IP. So, this bus architecture for the de facto standard what does that mean? It was originally designed for the use of ARM only with ARM and it was later on made as a open standard ok and it became a de facto standard that any you know its not that this is only standard there are other advanced microcontroller too. But for the ARM product ARM module a AMBA architecture will be issue with a open standard, this can be used not only to connect these which are coming from ARM it can built their own IP and interfaces . So, that is the way this market grow and presently. So, this SoC making an SoC with these interconnect along with this chip is modules is what is a aim for coming up with this standard. So, the low power design and the performance in terms of when you say even bus is there and then you know we are talking about performance is the bytes per second ok. How many how much of bytes can be transferred over this per second? That is one that is bandwidth ok of this bus. Another one is a latency, that is suppose memory MMU is connected to memory ok and memory is of course, connected to the bus, if it is on chip memory ok then it could be an interface could be there with the bus and then connecting to the off chip memory. Now latency is what? When an any address is sent out ok by the processor how long does it take for a maybe for a recycle? How long does it take for getting a data getting the data that from memory to the processor. So, this is the latency and how fastany data can be transferred over the bus is what is bandwidth and how many devices that could be connected to this ok to the bus that is another design capability. If there a some limitations on number of module that could be connected to it, then there will be some limitation right. So, how many can be connected that is how adoptableor how how easy it is for equate to bridge their IP and connect it to the bus without impacting the performance of course. And then what are the features are supported ok. In any bus communication I told you earlier that there could be one master at a time, but it does not mean that only ARM can be a master in the whole bus ok. There are other IP like DSP processor could be designed, and then that could be a master for its own transaction on the bus and ARM could be what? And then that could be a DMA moves initiating the transfer, but even may be peripheral to MMU memory. So, this kind of multiple masters could be there in the system. So, this design should support multiple masters being in the system without completing. Now they will also be completing for the bus ownership, but it should be controlled by somebody ok that there should be some control logic in this bus, for the for the masters multiple masters connected to the bus to transact over the bus. So, that is should be a speciality. So, may be arbiter is one which I will talk about bit later, but that give me overview an arbiter is the one who decides among multiple master connected to the bus ok who can own a own the particular busyou know the bus for a transaction at a particular time. So, what I am saying is, maybe you know time t 0 to t 1 ARM can transfer over the bus and then from t 2 t 1 to t 2 may be DSP processor which on the bus can transact over the bus and then later on may be DMA transfer could happen. So, who decides who is the master at a particular time? Arbiter that is the logic which is the centralized arbiter who is theor module is connected to all the masters in the chip, and then there it is only connected to two things ok two signals. One is a request and another one is grant. So, every masters who can initiate transaction over the bus or connected to the arbiter, and then they communicate to the arbiter before they transact over the bus that mean they should be grant us access to the bus and they do it. So, that facility should be there and then there should be a if you recall the non sequential access sequential access, that we saw for the while talking about memory interfaces and different instruction how much time they take, we say that ok one nano non sequential access comes to sequential settings so; that means, what? Burst transfer burst burst transfer should be supported; that means, the initiator gives one address ok; that means, address is a first address is given then the subsequent addresses are all to the you know address relative to this ok. If the bus width data width is may be 4 bytes ok then plus 4 every address plus 4 will be transacted; that means, multiple byte multiple words over the bus starting from some address. So, that is the burst transfer that is called a burst transfer. And then that that be a split transaction; that means, when we have multiple master trying to transact over the bus, one option is to say that ok one master communicate and then it finishes and then next master communicate with whatever slave and then it communicate with transaction. Another one is each master initiating some transaction and then may be this initially it was initiated then this that done for some time, then other master gets the bus and the data gets another. The transaction is split across multiple type. So, spilt transaction that is the another feature of a bus. So, maybe that is another feature that would help in making sure that the bus is always intellect because whenever any memory is to be accessed, it will take its own speed time for decoding the address and then coming up to the data. So, during that kind of cycle may be some other master can be allowed to use the bus to initiate some other transaction. So, the may be may be with the peripheral or it could be with some other external memory. So, the same memory is not involved in the case may be you know we can parallelize the transaction that is happening on the bus. So, spilt transaction, burst transaction burst transfer and then low power. So, there should be some features which is start up the bus to handle the low power design that mean this transaction order bus do not consume a power or when there is no transaction the bus is now not consuming power. So, these kind of a different features are built into this SoC, this particular AMBA architecture and then released for so, that to be used within the SoC. So, please remember this this is not outside the SoC it is within the SoC. You might have see you might have heard about so, many other bus standards like multibus or ISA ok ISA in the PCA bus you would have seen that ok PCI ok peripheral component interconnect and then multibus ok. These what are the difference between these bus standards and what we saw what we are seeing here? Now we are going to see here. The AMBA bus is within the SoC that is within the chip whereas, the multibus ISA and PCI they are all over the racks may be different or PCB ok within the PCB on the mother board you can see that ISA and PCA standard for there we plug in some PCA bus add on process. So, communicate with the motherboard or the PC ormultibus is something like backbone ok kind of a rack ok. So, that plane there are bus address bus data bus it goes on the backplane and then the cards go into the crack. So, this is kind of a multibus standard which is you know which was given by . So, this this standard bus standards wait for either PCB or backplane kind of an environment whereas, AMBA standard is for within the SoC with some on chip hopethis introduction gives you some overview of what we are trying to do in this ok. Now, this is for the connection and managing the functional blocks in a system on a chip ok it is connection as a management of the functional blocks modulus. It facilitates right which facilitate right first time development of multiprocessor design with the large number of controllers and peripherals. So, the SoC what we are trying to build using this standard is not limited to one or two, a multiple peripherals could be there, controllers could be there, multiple processor masters will be there on the chip and the AMBA architecture is adaptable for at a complex design and it should be easy and it should impact first time. So, to enable this there are some features provided along with the AMBA specification the testing feature ok. You could test any module independent of auto modules in the system in the SoC and then interconnected with the referral chip. So, a testing also its part of the design specification and that there are features available supported in the AMBA architecture So, AMBA promotes design reuse that is very important. Because anyone designing a graphics processor may be which is AMBA come to an end ok graphics processor. Then it could be used not only in one particular yes you knowcomponent SoC this could be sold to different vendors and it could be caught up different SoC. So, this is the interfacing layer for those AMBA standard any any SoC which is which follows AMBA standard this SoC could be reuse there without any problem its like a pattern plane kind of a scenario. So, that design reuse is the most important thing for request adaptation of this particular standard for the SoC design. Wide adoption of AMBA specification throughout the semiconductor industry has driven a comprehensive market for the third party products. So, that is what I am trying to tell you a design reuse type plane getting different IP third party the IP product, which are AMBA comprehensive where there is the plenty of IPs coming from different vendors which has AMBA comprehensive because there are lots of solution with a ARM based and this is the IP products can be interconnected with a without any issue. So, it actually h a coming up with a different SoCs with the multiple features and the SoC vendor also the semiconductor company can differentiate their design from other competitors by integrating their own IP at a third party IP which are AMBA comprehensive and then follows AMBA specification or interfacing or connecting the multiple modules within the chip. So, which sells both the buyer as well as the vendor for a quick market time to market as well as easy to integrate and then in development is easier and test is easier because all the features are there. So, this has enabled availability of good support for the development of AMBA based. It could support in the ecosystem ok that is very important for any product to be successful in the system in the market. So, good ecosystem was developed around the AMBA PC . Now, what are the IP re use write a advantage? IP reuse requires a common standard while supporting a wide variety of SoC. So, there should be a common standard, but it should not be restricted restrictive if it is restrictive then too many PC may not be willing to reuse IP. So, the common standard allowing multiplevariety of wide variety of SoCs supporting this wide variety of SoCs is the the most successful feature of AMBA . So, with a different power performance area required. So, SoCs with different requirements see you may be interested in building a in SoC for a 16 bit microcontroller for a very high very very low power design low power environment may be a you know aeronautics or may be it is for a small embedded system ok in the system phase come you know phase maker or something like that ok or it could be a big router with a powerful you know performance requirement ok a high power performance at high performance requirement in SoC it could be built. So, the AMBA specification should be generic enough or either or either a very low end16 bit or even 8 bit controllers as well as 32 bit or 64 bit bit process known systems. So, and high performance. So, this kind of a this these two are very very wide requirement right, but AMBA specification needs it so, that is why it is successful. And AMBA is a coherent hub interface with anotherstandard you know AMBA 5, interface ARM you know that interface ARM extends performance and scalability to many coherent processors. So, this is not even restricted to only single processor environment even multiprocessor environment with chi next level of specification of AMBA helps you in having multiple processor in the system ok. Cache coherency and then you know multiple processor are its own cache l 1 and l 2 maybe l 2 cache memory common then there should be cache coherent built into product. So, those kind of features have to supported. So, the CHI takes care of that. And multilayer architecture acts as a crossbar switch between masters and slaves in AMBA 3 system. So, multilayer systems in terms of area ok when you have that interconnect going over multiple layer the effectives area occupied with a bus comes down and the width of the bus see it actually this AMBA bus varies in terms of bit from 8 to 1024 bits ok. The data bus width of the AHB bus could be nearly in trans 8 bits 1024 bit this is a very very wide support in terms of number of data lies in the bus. So, if we need to support this without pattern pasting on the area as well as signal integrating issues, there should be some design kind of multilayer architectures which will help you in terms of achieving the speed that is required for making a performance and without sacrificing on the area or the noiseon the bus. So, availability of the system will be better when you increase the speed of the transaction over the bus. So, that should be some design elements built into the system. So, that it is also there. So, the parallel links allow the bandwidth of the interconnect to support the peak bandwidth of the masters without increasing the frequency of the interconnect. See when you have a multiple layer then you can increase the data width once the data width is increased then without increasing the stoke rate ok without increasing the stoke rate that bandwidth can be increased. Because within one clock cycle ok so, much of data is getting transferred. So, we get the peak performance peak bandwidth without increasing the frequency of the interconnect so, that can be achieved. So, AMBA promotes design reuse by defining common interface standards for SoC modules. So, this is the very important again I am reiterating that, it is a common interface standard for SoC module ok good. So, before we get into the some bus titles and their interfaces let us see the what are theconventions this all of us are cleared and there are there is a grey area, the value of the bus NH 100 is not defined ok when there is a transient glitch in the bus and the bus it will be interpreted like this which is expected ok. And then when a bus from either from highly or low is is becoming a low sorry high becoming a high this is visible into then bus is shown like this ok particular time in ok these are all at particular time t. So, the value could be 1 or 0, but it is a stable state ok it is completely stable it driven properly and highly impedance state; that means, there is a very important property of supporting a low power design. Because once the bus is on high high impedance nobody is driving the bus. So,it is not drawing the current and its capacity expect on the soc and the system is also less . So, high impedance state is shown like this and any bus in change in the signal is shown by this particular pin and when it is coming from high impedance to stable state it will be changing ok for a moment and then impedance stable bus like this ok these are the different signals. Shaded bus and signal areas are undefined. The bus or signal can assume any value within the shaded area ok it could be 0 or 1 or it could be even you know some intermediate values ok not getting anyone, we do not bother about no module which is connected with bus will bit transmit at this time. So, it it is take is nothing no other module will go a real anything corrupt corrupted data doing with that. The actual level is unimportant and does not affect normal operation, that is what I am trying to say it does not affect a normal operation any objective modules connected to the bus ok. Let us now see a a overview of the AMBA ok let us look at some more details about AMBA. So, it was introduced in 1997, AMBA has got two levels of hierarchy I have already told you this ok ok Advanced High performance Bus or ASB. So, this is one level ok another one is advanced peripheral bus. So, now,giving you some more the AMBA is a standard architecture that is the multi microcontroller bus architecture under that different bus standards are there ok. So, either AHB or ASB will be in a system and APB will be there, I will give you a demo. I will show you a diagram where you will understand what is this peripheral bus this is for a low power low performance ok peripherals to be connected and when a a low performance bus is connected to a peripherals are connected to a directly they are connected to the high performance bus, because of the delay in the of the peripherals intersystem the performance of the high performance bus or the the transactions on this bus by high performing modules like processors. And memory wont memory is not high performance that appears you know with a got very good you knowaccess time, no will be delayed because of the presence of this. So, that is why they divided this; so, low performance and low power device you know not only low power actually low performance peripheral which are slow peripherals are do not connected to the high performance bus. That way because of the low speed peripherals the highly you knowthehigh performance bus and the modules connected to them almost slow down ok that is the purpose of two levels. On chip test access that is a very important which I mentioned built in structure for testing modules connected on the bus. So, this is helps in time to market and a minimum of 32 bit data operation is recommended in the standard and it is extendable to 1024 bits ok. Minimum of a 32 bit is recommended, but 8 bit also you can provide the 8 bit data bus ok. So, this is thehigh level overview of AMBA. Now, let us lets I will I will tell you what all thesome idea around high performance bus ok here ok. So, in this AHB bus sorry ok the AMBA AHB is a high performance high clock frequency system modules system modules ok high clock frequency system modules are connected to the bus. AHB acts as a high performance system backbone bus ok. This is the bus which is used for connecting high performance and high clock frequency system modules. AHB supports efficient connection of processors, on chip memory and off chip external memory interfaces. So, the different processors in the system SoC when I say system is SoC ok because this buses are going to be interface SoC. So, you know if you have a multiprocessors and this is actually supports multiple masters in the system. So, AHB supports multiples masters. So, you can have multiple processors in them and they are all connected to the AHB bus and on chip as well as off chip memories are connected external memory also connected to the same AHB bus . With low power peripheral microcell functions. So, this low power peripheral microcell function also there, but may not be connected directly it could be through APB bridge that I will talk about later. AHB is also specified to ensure ease of use in an efficient design flow using synthesis and automated test techniques. So, it also has P wave design slow. So, that you will be able to integrate the modules different peripherals or differentprocessors or or memory in the SoC . Now, what is ASB ok? Advanced System Bus the AMBA ASB is for high performance system modules ok. Actually this is at either AHB will be there ok in a system high performance bus oris we do not want in a system where this kind of a high performance is needed because this complexity is more and power consumption will be more and it meant for a high clock rate peripheralshigh clock rate processor, but if; that means, the complexity is not needed then designer can chose their ASB there instead of AHB either this or this right anyone of them. So, AMBA ASB is an alternative system bus suitable for use where the high performance features of AHB are not required and ASB also supports efficient connection of processors on chip memories and off chip. So, whatever AHB supports ASB also supports, but this is the meant for a low performance systems. So, naturally it will vary or requirement will be less compared to this comprehensive integer here and power consumption also will be there. So, this is the designer choice we have to figure out to use AHB or ASB. What is APB is Advanced Peripheral Bus, AMBA APB is low power peripheral this for low power peripheral is optimized for minimal power consumption and reduced interface complexity to support peripheral functions. So, the interface simpler is not complex design and minimum power consumption. APB can be used in conjunction with either version of AHB or ASB. So, APB can be this used along with either of this ok. As I told you where processor some memories will be using these buses; that means, they will be residing on this bus and all low power peripherals will be on APB. So, they can be APB could be used along with this objects. A compatible bridge either AHB, APB or ASB, APB module is used for connecting the APB. So, that is should be a bridge. As I told you a high performance bus cannot be connected to a low performance bus directly. So, there should be a bridge I will tell you why it is required and how it helps in satisfying both the requirement ok let us hold on. Now, before that let me give a get a small overview of what is a macrocell ok .those who are not from design background we will be able to appreciate this. So, if ASIC is a chip which is made with custom made for a particular application ok the name fairly mentioned that application specific is a integrated chip a macrocell array is an approach to the design and manufacture of ASICs ok its one way of doing ASIC may be not the complete ASICs may be a part of it. So, essentially it is a small step up from other similar gate array designs ok Gate array is it will be provided with a different case ok and then may be more NAND and NOR gate will be there ok and then of course, some buffers and you know invertors and all that. So, these kind of generic gates will be provided and then they will be connected according to the circuit requirement you may realise any circuit using different generic gates or may be a specificNAND and NOR gates are you know you know then gate, but they will be requires to other gate also to this you know implement a your final system a circuitry which is the gate array. Rather than prefabricated array of simple logic gate, the macrocell array ok is prefabricated array of higher level logic functions; that means, instead of designing you know having an array ofyou knowsimple logic gate, it is a prefabricated higher level logic which are they? Flip flops or ALU functions or registers and the like. So, now because there are registers may be there and then you knowyou knowmay be flip flops will be there ok. So, this kind of thing may be okor ALU functions ok. So, multiples may be one not one or two multiple will be this and then how they are connected is what is decided during the later stages ok. So, so macrocell enables in building such a solution with a basic functions which are high level value These logic functions are simply placed at regular predefined positions and manufactured on a wafer a standard cell library is also sometimes called a macrocell library. So, they later on they are interconnected to realize the final functionality, that is required ok this is just its give you a overview of what is the macrocell fine. Now, typical AMBA based microcontroller before we go into the detail of each of the bus and how bus transact happen, let me tell you a typical implementation of graph. This is the one SoC ok which is having both AHB or ASB bus and AHB bus, and it has got a bridge bridge between a high performance bus and a low power low performance bus. And what are these devices? They are all devices which has got very very low bandwidth band you know bandwidth devices. Where the data generated by these devices are all comparatively very very low rate ok very low rate you can imagine you know how many key key entries can be generated from a keyboard is basically our ourlimitation on how many keys that we can press and this may be different you know may be it could go up to kilowatt rate, but still it is not as big as gigabyte range of transaction that happen over this bus. So, here they are 2 byte or may be kilobytes of data, get to gigabytes of data transaction that second of course, ok. So, you can see the difference between these two and you know almost around t10 power 6 ok. So, let say the bridge is coming in it let me this is the right time may be I can decide no I can tell you something about what is the functionality of bridge here. So, both suppose if any of the processor ok this is the ARM processor and then there is ARM chip ram and then a DMA and external bus interface memory so, memory external memory connected to this interface. So, this could be a master and this could become a master and of course, this will be a slave memory and this will be a slave in the AHB bus or a ASB bus. Now, this master ok master is one which initiates transaction of the bus and slave response with the that whatever the master asked for. Now this master could communicate to a peripheral also. So, you might have written some code or may be a device driver interface with you know connecting to the UART task now the ARM processor is starting to the peripheral means or you are trying to write one character into the bus into this particular register which needs to be UART will be connected to your p c may be ok let us assume this is the PC is therea TSD RSD ok these aretransmit and receive ok data flows in this way and data flows here. So, characters will be sent over the serial bus ok some baud rate may be ninety 9600 baud rate 11 points 11 kilo. So, 96 9600 this is 100 maybe we can say that this is the baud rate. So, every character may be generated by this processor and then it is writing into the UART. Now, what happens? UART is a very slow device. So, connecting into that if it waits for UART to give back acknowledgement it will be unnecessarily holding this bus for long which is meant for a 2 giga bit of transfer. So, it is not your choice to make this bus wait for some transaction over with a low performance devices low data rate devices. So, to remove that particular delay in transact you know in interfacing with the what you know talking to this devices there is a bridge here. So, which is actually helps in buffering the data which is coming from either here or in this direction and then completing the remaining transaction. So, the ARM processor if you wants to write into the UART, it write into this and then bridge say that ok I will take care of this a particular UART. So, you can go go ahead with the transaction. So, the transaction gets completed here and it can communicate with the bus memory or it can caught up to this or you know it can initiate from DMA with a memory whatever it can do. So, this bus is speedup for the next transfer while this bridge is helping in terms of completing the previous transfer that all are neglected. So, that is a job of a bridge ok. So, APB bridge is always connected to the AHB AHB or ASB through a bridge so, that it does not in fact, the performance of this bus ok either this. Let you previously let me tell you what each bus features are high performance of course, pipelined operation what I mean by pipelined wave when an address transaction happen ok. If the bus transaction actually you can split it into multiple pin for address and data ok. Suppose if it is a recycle address will be generated after sometime the data will come from memory. So, in a pipelined operation well address is generated for the previous cycle and the data is yet to come, another address generation could happen. Get the transfer for another transaction that you knowsomething do with a we can overlap the operation that is basically you know typical to pipeline in the instruction, where one instruction will be in a fetch stage and another instruction will be in a decode stage and another one will be in a execute stage, the bus transaction also can be in different stages. So, that is called pipelined operation. So, because of that the efficiency of the bus is invoked. So, the bus is not idle at any time waiting for some memory to respond because some other transaction can be initiated. For example suppose ARM wants to you know write something into this bus or read from some this memory, it will take some time for it to respond that to the data. By this time may be DMA can initiate some transaction with this external bus. So, address can be put here and it will be resolving that address for it to write something from may beyou know from RAM to you know external RAM or from some other peripheral here connected that another processor here. So,some other memory ok a macro memory to or peripheral to memory whatever it is. So, when multiple transaction happen it could be pipelined so, that is what is the advantage of the AHB bus ok sorry. So, multiple masters could be there. So, another processor can be there. So, this could be a master or ARM could be a master or DMA also could be a master burst transfers are possible; that means, one ASCI question cycle forward by multiple sequential set spilt transaction is possible multiple transactions can be split and they can be executed. So, the effective data idling time of your bus is minimized ok that is the features of AHB. ASB similar thing. So, you see this only these two are not there in the ASB because it is a complexity is less and is for low performance devices where you do not want a complexity of ASB then you can go into the ASB ok. Now what is APB Advance Peripheral Bus which is a low power latched address and control simple interface and suitable for many peripherals. So, now, you can multiple peripherals can be connected here ok these are the latched address control very good. So, now let us go into some more details of AHB. This is the typical bus transfer of AHB bus. You see here everything is appointed with head to stay which is AHB signal ok and HCLK is the similar to MCLK we saw ok main clock in the ARM HCLK is for the AHB bus with the main clock. So, initially it is address phase and then the data phase in the clock. So, address is putting assume that its a read data ok. So, write data it could be a this is showing you a write data what what is happening and the read data ok. And here what you assume is the data width of 32 bits ok it could be as I told you it could be varies from 8 to 1024 bit. So, in a transaction in a transfer 1024 also bits also in one transaction, but they recommended is 32 bit And then what happens is during in address phase address is given ok and then the write data is available in this data phase when after this HREADY ok by the. So, memory with with the processor this is coming from processor suppose this is coming from some memory sorry master, it could be a ARM processor ok it wants to transact over the bus with the memory. So, slave is the memory correct. So, if you if you wants to write a data into the memory. So, the memory has to tell whether it is ready to accept the data byHREADY is the positive value. So, when it becomes high it means that it is ready to accept the data. So, when this is made high then the data is put. Now, suppose in this clock cycle also if this remains continuous to be low what will happen that is called wait phase. Because the memory wants to add more wait phase because it is still yet to decode the address or the memory is the slow device, it is the low you know performance memory. So, in this case it can you know it will put some wait case by extending this it will not make it high and then it will delay the transaction. So, the master ARM has to wait for data available until this goes high when this goes high in this way ok clock way. Then when it becomes low the data is made available and the memory can fetch that during this time it it will take a you know data which is available on the bus and then it will bring down this value. So, if it happens to be you know sequential access may be it will continue to how hold it and then it will give you the other data that I will show you later and what about this? This is for reading the data. So, when it says that I am ready to provide the data, then the master can read the data from here. So, it is showing the write data from master to slave this is the reading a data from slave by master ok. So, the data will be available when the HREADY ready from the slave is made high I hope this is clear to you this particular transfer. Now, I mention that there is a centralized arbiter in the bus why is it require? Because multiple masters are supported in the AHB bus that should be an arbiter. If there is there was only one master in the system then there is no need for an arbiter. So, this is only what is going to be initiating any transfer. So, this master is in control of the bus and it does not have to worry if anybody is using the bus or not. But once there are multiple masters in the bus, then everyone everyone is to make sure that the bus is free for the master to transact over the bus. So, to unless otherwise there is somebody who is centralized and come you knowlooking at transaction happening over the bus, the individual masters may not be aware of what is going on. So, that is why the centralized arbiter takes care of GB access to the bus ok. So, it can even associate somesome master as a default master; that means, if nobody else is asking for the bus the default master will be given the control of the bus. So, if the default master will be suppose this is the ARM processor maybe we can make it as a default master that is considerable. So, if no one else wants the bus, this will be given otherwise there will be a priority and then accordingly the arbiter decides about who will be have having the control of the bus at any particular tangent time . So, this kind of what all the you know interfaces with the arbiter and the master? There is abus requests coming to the arbiter ok requests coming bus request is coming from the master to the arbiter and the grant going ok grant going to the particular master. So, how many such lines will be there? With every ok master there will be a request and grant connection ok one will be in this direction, one will be in this direction ok request and grant. So, arbiter gets all the request from everybody every masters in the system and then it which choses one of them based on some priority ok and then this access to one of the master. So, grant will be only one may be it has chosen this, then only one master will get the grant and then they when the master will drive the address or data based on whether it is a right cycle or maybe it is wait for the data if it is a real cycle. So, this is how the AHB bus ok connected to by different masters communicate over it with a different place in the system. So, what is the order? Before any master wants to transact over the bus they need to get the permission from the arbiter which is the centralized arbiter looking at all the request coming. So, all the masters should be connected to the arbiter like I just told here and then they will be granted bus at a particular time. So, what happens? One of them will be based on the choice, one of the address coming from any one of the master will be going to the bus and then based on a choice again the data driven by ok data driven by any of the slaves will be going to the particular master ok. Only one will be driving anyway one of the slave because based on the address one of the salves will salves will respond and then it will be given to the particular master and this not takes care of, multiple takes care of, choosing the particular master based on the grant given by the arbiter . And then what happens the decoder?The data coming is decoded and then it is given to the particular master ok read data master. So, this is the this is how the interface is between between the set of slaves and the set of masters in the AHB bus ok I hope this is clear to you So, AMBA AHB bus protocol is designed to implement a multi master system unlike bus architecture designed for PCB based systems, the AMBA AHB bus avoids tristate implementation which avoids tristate implementation where which is not a PCB based system ok. So, the bus is not going to be on the PCB, it is going to be on the inside the chip. It employs a central multiplexer interconnect scheme ok. So, it is not the that other devices need not have to be in a tristate on the chip because there is a master in the system, It provides higher performance and lower power than using tristate buffers. So, because of that performance is better and the low power also interface. Because if it is tristate you know every device use to drive the bus, it will take some time for charging the busbecause of capacity website there will be, the time taken for signals to stabilize on the bus will be longer ok a typical tristate system. Whereas, if it is a much place system everything is actually connected, but power may be a problem, but the thing is it will be easier for in terms of occurring the top rate ok performance. And it is a low power than using the tristate buffer okbecause there is not so, manycharging or recharging you know disturbing of the buses. So, because of the power this this take a or buffer power consumed by the buses of the signal over the buses will be minimized the transactions are does ok. If number of transaction over the bus uh is reduced then thepower consumption will be less. All bus master assert the address and control signals indicating the type of transfer each master requires and then central arbiter determines which master has its address and control signal routed to all the slaves. So, you know arbiter determines or choses the particular master ok grants the bus for a particular master then that master controls on their control signal what is the control signal? That is control signal talks about whether it is read or write whetherwhat is the bit of the transfer whether its you know half power transfer or full power transfer okor may be a byte transfer. So, this kind of a different thing can be communicated over the bus. A central decoder circuit selects the appropriate read data and response acknowledge signal from the slave that it that is involved in the transactions. So, particular responding you know data coming from the slave device, that will be connected to the a master who is grant who is holding the bus. So, may be who has initiated transaction. So, that person will be that master will get the data coming from the slave. I hope this is clear to you. Now, data transfer its a pipelined or tenured bus. So, address phase of any transfer can occur during data phase of previous transfer sorry its overlapping; address and data phases ok of different transactions are overlapped. This is what is called pipelined or tenured bus because of this overlap performance of the bus is improved ok. Now, what is the retry? Suppose one one transaction suppose you know it has got a non sequential address, first address is non sequential and then remaining addresses are sequential; that means, one disk transaction is done then next address could be then plus 4 may be you know based on the peripheral data or whatever a data bus. So, that kind of shown ok. So, this is the indicating as the what types of transaction is happening non sequential or sequential ok and then why is it idling now? It is idle signal is generated when the slave response will be RETRY or it says that HREADY is low; that means, the after this transaction was completed ok HREADY is low; that means, the peripheral or the slave devices write that that I am not ready to accept the next transaction. So, because of that okthere is a retry; that means, the data what was initially given ok the address and the data what was given is not may be written into the memory properly may be there was some problem, may be there was a corruption in the data, but whether may be aparity check would be there, and then may be because of a bridges on the bus that could be data could be corrupted and in the case that device memory device can initiate a read write; that means, the same data is again address and data may be put on the bus for that to be accepted by the slave . So, theI am giving the retry example here and then burst transfer the you know we can have a multiple transaction for a first non sequential address. So, different addresses are given now I have to see that ok. And if you see there is a burst transfer that signal is grant; that means, it is communicated with the devices that the burst transfer is happening and then a different data for a specific those addresses are given from the bus ok. So, they are all the you know provided again you see here it was ready in this state and then it became low and then it becomes continue to be 5; that means, it is ready to accept the data continuously. So, because of that becoming low you see this 38 is coming again ok it is kept it for long and then this data is coming here ok. This address is given this is delay actually and then because of that you see that this transaction it also taking more cycle, after that the cycles are one clock only. This is taking two clock cycles because this device or slave device are send back and not ready to take take that particular transaction because initially the non sequential cycle takes no time. After that the rest of the accesses will be slow down you know faster for sequential class cycle then spin circuits will will get more time and I know it takes more time and then it will selects as become fast later on. So, it clock occurs in all the data coming later on. So, this is one typical examples of the signal transaction Iif you know if you are not able to follow this, this for shift for a while and then understand the sequence because this is very important to understand how the different signals are helping in terms of transacting over the burst. Now, what is the split transfer now? What happens is one during one transfer ok a grant signal is withdrawn ok and then for a slave signal to split and then arbiter changes the grant ok. Now new master drives the address; that means, once the slaves say that the one master is communicating and; that means, one master is communicating that one slave ok may be call it as M 1 and S 1. Now, S 1 says thatyou know slaves signals are split transaction, I like to have this transaction to the split; that means, this transaction bus cycle is terminated for a you know intermittently and then during that time the arbiter could give the burst to another transaction, but even a master and the slave . So, new master drives the address so, that is why you see that another non sequential address is happening, in between there is an idle cycle because the arbiter take some time to grant the particular bus and the master has to drive the bus. So, this cycle is used for arbiter to chose the another master and then communicate to the master. So, that the other master there should be something pending ok some grant you know requested pending so, that the arbiter could give a new master. So, do use the bus and then it is generating another address this is coming from another different master and a different control signals and the transaction happens. So, the split transaction is communicated for breaking your transfer transaction happening and then the arbiter decides and then gives the control to the bus to some other masters. So, this is one typical example of that. So, what are the bus width scenario? So, one way to improve bus width without increasing the frequency of operation is to make the data path of the on chip bus wider. So, this is possible I told you this; however, it is recommended that the minimum of 32 bits used or maximum of 2 because even even increasing the bus width to this is a better bit you know though it improves the performance, there are stability reliability issue might be there. So, the recommended bits are this 32 and 256. For both read and write transfer the receiving module must select the data from the correct byte lane on the bus. So, as a when if you remember you know if the byte transfer is happening may be particular you know odd odd address or even address, a particular word a byte sorry this is the word ok before allbytes ok. If suppose it is writing onlythis byte some may be the same value can be driven on all the buses ok and then I was telling earlier that you know based on the memory which is there, it could take this value and then internally it can write into the particular location in the memory. But this actually driving the same data over the multiple buses actually improve increases the power consumption. So, in this case in the AHB the correct byte lane on the bus needs to be driven. We do not have to you know replicate the data on all the byte lane ok. So, the module must select the data from the correct byte lane. So, in the various any peripheral or a slave connected to the AHB bus should be capable of getting the byte specifically based on the address, uh you knowwhich byte lane has to be used for reading the data this slave device should be aware of and then it should do it accordingly either reading or writing ok replication of data across all byte lanes is not required ok. Now, let us sketch upon it will not a small introduction to APB. So, APB has three states one is idle state and had setup state and enable state ok. So, these are the signals it will be in idle state where nobody is driving the bus ok no power is learn, and it is all the devices are not into transacting over the bus and then if anyone wants to drive on the bus, then if the single setup phase and then based on the multiple transaction happens then it will be in enableand then setup phase it will go into this. There is no transfer is there then that you know state of the bus goes to idle state ok. This is the kind of a state transition and this is the selected particular peripheral device will be selected if it is one ok and then what will be enabled this transact over the bus. So, here if you see all the signals are updated with the P; that means, it is its told that it is the APB bus signal whereas, AHB signals were given which has a prefix. Now, APB states idle state the default state for the peripheral bus setup. When a transfer is required the bus moves into the setup state where appropriate the select signal is asserted only one will be asserted ok. And then the bus only remains in the setup state for one clock cycle and will always move to the enable state on the next rising edge of the clock. So, once it is setup it is actually one particulardevice in the APB bus you know peripheral is selected, then it will be in a setup state afterword it will be in enable state. So, that is peripheral will be either reading or writing to the bus. So, enable in enable state what happens? The enable signal P enable is asserted and the address write select signals remain stable during the transition of from setup to enable. So, either write or select signal will be active during the time . So, this is the critical transfer transaction over the APB bus, this is the clock this is actually a low you know its not a frequency clock. So, address is given ok it is valid here and then the write signal is given, that is writing into this address with a particular data ok and then a particular peripheral is decided selected and then enable. So, this is the from idle state it enters ok ok. So, ok yeah. So, what happens? It is in the idle state here and then it entersetup state and then enable state. Once it is enabled it is in enabled state. So, this is the setup state setup this is enable state ok and then this is the idle state. So, now, we may wonder, why is it address and the write signal continuity to be this idle where they not driven look. In order to reduce power consumption the address signal and the write signal will not change after a transfer until next access occurs. See as I told you when there are not you know signal transitions, then the power consumption will be consumption will be reduced. So, to keep that and it is not tristated as you remember this is not tristated bus. So, the peripherals need not be taken off from the bus of the bus need not be tristated. So, the other signal will remain other whatever the earlier cycle whatever the address put on the bus will continue to be there on the bus until the next select is happening and then the next address is put, till then there will be same address and byte signals will not maintained. So, that is the read transfer this is the read, that is the write transfer this is the read transfer. So, the data is comes in late ok . So, the device is selected and then enabled, and the data is driven by the peripheral device ok master read from the slave read write read transfer I hope this is clear to you very simple. So, APB bridge. So, this is the kind of a APB bridge which I have mentioned. So, all the you know the P P data and the rest all this all connected to this ok and then the system bus to the system bus either it could be ASB or AHB ok this particular APB bridge looks like a slave ok. So, that is why the slave interface is connected. So, the ASB bus or AHB bridge will be on this side connected to this. So, we are not showing any of the state signals here ok they are all here. So, it is the from the AHB bus this is one of the slave device and then rest of the signal are all on the APB bus side. So, APB bridge is the only bus master on the a p AMBA of APB ok. So, AMBA APB APB bridge is only bus master in addition the APB bridge is also the slave on the higher level system bus. So, on the APB side the bridge is the master ok. This this is what is going to actually mimic any transaction happening between the devices on AHB cycle to APB peripheral. So, actually this is the master as far APB is concerned sorry APB on the APB bus the APB bridge is the master whereas, on the AHB side this is the slave. So, this is AHB side okthough the signals are all from APB and this is the APB side suppose if you take, it begins like a master on this side and begins like a slave on this side. So, whatever data is coming from AHB is buffered here and then later on deliver by choosing a particular one of the devices slave devices and then this is generating these would address would have come from this right. So, it will based on this address, it will now bridge particular device is selected and then it drives to same masters here may be modify let me bit if it is recommend and then your particular peripheral device will be selected and the data whatever given suppose it has got read ot sorry write, the data is already buffered and the address is also buffered both will be driven driving here. So, by the time thismaster who was actually originally driving this, would have gone into completed the transaction and some some other transaction may be happening on the AHB side. There are this is still going on on the APB side, that what is the advantage of having a bridge. So, with this we have come to aend of this session which talked about all the a AMBA architecture, this is the very very high level overview of this buses ok.I think with this introduction if you can read with based on your intent or based on what you are trying to design hardware, either as a hardware designer or as a software embedded software developer. You should be able to read through all the manuals of learning different buses and understand more details about, how certain things need to be interfaced ok in a SoC ok. So, I am very happy to share this with you I hope this was useful to you . And see you in the next lecture may be looking at one of the peripherals with. So, we will be talking about some peripherals in the next lecture ok have a nice day. Thank you very much for your attention; bye bye .

Hello friends. So, welcome you all to the
ARM Based Development course session 32. In this session we are going to be covering
AMBA architecture ok. So, this is a different from whatever we have discussed so, far this
is about the DAC interconnect ok. Let me nudge it. So, we will be covering some
overview of what is AMBA architecture is all about and then I will show you a example structure
of an AMBA architecture along with ARM processor in it and then we will go into the details
of AHB and APB feature AAP APB bus and what are the transactions and signals.
And then APB bridge also in some other modules and related to the AMBA architecture.
So, before we come from to this discussion I would like to give you some overview ok.
What is this specification and why it was designed by ARM? This is the interconnect
standard from ARM ok. So, what was the motivation how does it help
in our design of primary resources which is AMBA.
So, let us look at that introduction part, AMBA is a an acronym of advanced microcontroller
bus architecture it is the de facto standard for on chip communication. So, what is the
de facto standard ? Suppose you have ARM core and then when ARM
define this processor and then we have model business model versidue on at an high speed
and then they also gave other IPs like cache controller right and then MMU MPU ok. These
are all something which is these are all this this this modules are going to be is a SOP
final SOP ok and then FPU. So, they define design different cache controller ok. So,
this will in turn will be giving instruction and then data caches. So, the design all this
modules at an IP. Now, having given this if there is no uniform
layer connecting them all together ok then there will be an issue. Because the performance
and power as well as cost everything that we gain using this modules ok will be actually
only when we have an interconnect ok. With this well design and meets the requirements
of the low power design that on its targeting that the that this is the low power IP chips
and for the applications low power application where mobile applications or tablet and any
other embedded low power devices. So, the target market is this kind of a environment
ok this kind of a products. So, it is not enough if only this IPs are
given, but there should be some standard interconnect also defined around with this IPs then it
will be easier for people to buy this IPs and build their own IPs and interface with
the customers items or modules in the IP. So, this bus architecture for the de facto
standard what does that mean? It was originally designed for the use of ARM only with ARM
and it was later on made as a open standard ok and it became a de facto standard that
any you know its not that this is only standard there are other advanced microcontroller too.
But for the ARM product ARM module a AMBA architecture will be issue with a open standard,
this can be used not only to connect these which are coming from ARM it can built their
own IP and interfaces . So, that is the way this market grow and presently. So, this SoC
making an SoC with these interconnect along with this chip is modules is what is a aim
for coming up with this standard. So, the low power design and the performance
in terms of when you say even bus is there and then you know we are talking about performance
is the bytes per second ok. How many how much of bytes can be transferred over this per
second? That is one that is bandwidth ok of this bus.
Another one is a latency, that is suppose memory MMU is connected to memory ok and memory
is of course, connected to the bus, if it is on chip memory ok then it could be an interface
could be there with the bus and then connecting to the off chip memory. Now latency is what?
When an any address is sent out ok by the processor how long does it take for a maybe
for a recycle? How long does it take for getting a data getting the data that from memory to
the processor. So, this is the latency and how fastany data
can be transferred over the bus is what is bandwidth and how many devices that could
be connected to this ok to the bus that is another design capability. If there a some
limitations on number of module that could be connected to it, then there will be some
limitation right. So, how many can be connected that is how adoptableor how how easy it is
for equate to bridge their IP and connect it to the bus without impacting the performance
of course. And then what are the features are supported
ok. In any bus communication I told you earlier that there could be one master at a time,
but it does not mean that only ARM can be a master in the whole bus ok. There are other
IP like DSP processor could be designed, and then that could be a master for its own transaction
on the bus and ARM could be what? And then that could be a DMA moves initiating the transfer,
but even may be peripheral to MMU memory. So, this kind of multiple masters could be
there in the system. So, this design should support multiple masters being in the system
without completing. Now they will also be completing for the bus ownership, but it should
be controlled by somebody ok that there should be some control logic in this bus, for the
for the masters multiple masters connected to the bus to transact over the bus. So, that
is should be a speciality. So, may be arbiter is one which I will talk about bit later,
but that give me overview an arbiter is the one who decides among multiple master connected
to the bus ok who can own a own the particular busyou know the bus for a transaction at a
particular time. So, what I am saying is, maybe you know time
t 0 to t 1 ARM can transfer over the bus and then from t 2 t 1 to t 2 may be DSP processor
which on the bus can transact over the bus and then later on may be DMA transfer could
happen. So, who decides who is the master at a particular time? Arbiter that is the
logic which is the centralized arbiter who is theor module is connected to all the masters
in the chip, and then there it is only connected to two things ok two signals. One is a request
and another one is grant. So, every masters who can initiate transaction over the bus
or connected to the arbiter, and then they communicate to the arbiter before they transact
over the bus that mean they should be grant us access to the bus and they do it.
So, that facility should be there and then there should be a if you recall the non sequential
access sequential access, that we saw for the while talking about memory interfaces
and different instruction how much time they take, we say that ok one nano non sequential
access comes to sequential settings so; that means, what? Burst transfer burst burst transfer
should be supported; that means, the initiator gives one address ok; that means, address
is a first address is given then the subsequent addresses are all to the you know address
relative to this ok. If the bus width data width is may be 4 bytes ok then plus 4 every
address plus 4 will be transacted; that means, multiple byte multiple words over the bus
starting from some address. So, that is the burst transfer that is called a burst transfer.
And then that that be a split transaction; that means, when we have multiple master trying
to transact over the bus, one option is to say that ok one master communicate and then
it finishes and then next master communicate with whatever slave and then it communicate
with transaction. Another one is each master initiating some
transaction and then may be this initially it was initiated then this that done for some
time, then other master gets the bus and the data gets another. The transaction is split
across multiple type. So, spilt transaction that is the another feature of a bus. So,
maybe that is another feature that would help in making sure that the bus is always intellect
because whenever any memory is to be accessed, it will take its own speed time for decoding
the address and then coming up to the data. So, during that kind of cycle may be some
other master can be allowed to use the bus to initiate some other transaction. So, the
may be may be with the peripheral or it could be with some other external memory. So, the
same memory is not involved in the case may be you know we can parallelize the transaction
that is happening on the bus. So, spilt transaction, burst transaction burst
transfer and then low power. So, there should be some features which is start up the bus
to handle the low power design that mean this transaction order bus do not consume a power
or when there is no transaction the bus is now not consuming power.
So, these kind of a different features are built into this SoC, this particular AMBA
architecture and then released for so, that to be used within the SoC. So, please remember
this this is not outside the SoC it is within the SoC. You might have see you might have
heard about so, many other bus standards like multibus or ISA ok ISA in the PCA bus you
would have seen that ok PCI ok peripheral component interconnect and then multibus ok.
These what are the difference between these bus standards and what we saw what we are
seeing here? Now we are going to see here. The AMBA bus is within the SoC that is within
the chip whereas, the multibus ISA and PCI they are all over the racks may be different
or PCB ok within the PCB on the mother board you can see that ISA and PCA standard for
there we plug in some PCA bus add on process. So, communicate with the motherboard or the
PC ormultibus is something like backbone ok kind of a rack ok. So, that plane there are
bus address bus data bus it goes on the backplane and then the cards go into the crack. So,
this is kind of a multibus standard which is you know which was given by .
So, this this standard bus standards wait for either PCB or backplane kind of an environment
whereas, AMBA standard is for within the SoC with some on chip hopethis introduction gives
you some overview of what we are trying to do in this ok.
Now, this is for the connection and managing the functional blocks in a system on a chip
ok it is connection as a management of the functional blocks modulus.
It facilitates right which facilitate right first time development of multiprocessor design
with the large number of controllers and peripherals. So, the SoC what we are trying to build using
this standard is not limited to one or two, a multiple peripherals could be there, controllers
could be there, multiple processor masters will be there on the chip and the AMBA architecture
is adaptable for at a complex design and it should be easy and it should impact first
time. So, to enable this there are some features
provided along with the AMBA specification the testing feature ok. You could test any
module independent of auto modules in the system in the SoC and then interconnected
with the referral chip. So, a testing also its part of the design specification and that
there are features available supported in the AMBA architecture
So, AMBA promotes design reuse that is very important. Because anyone designing a graphics
processor may be which is AMBA come to an end ok graphics processor. Then it could be
used not only in one particular yes you knowcomponent SoC this could be sold to different vendors
and it could be caught up different SoC. So, this is the interfacing layer for those AMBA
standard any any SoC which is which follows AMBA standard this SoC could be reuse there
without any problem its like a pattern plane kind of a scenario. So, that design reuse
is the most important thing for request adaptation of this particular standard for the SoC design.
Wide adoption of AMBA specification throughout the semiconductor industry has driven a comprehensive
market for the third party products. So, that is what I am trying to tell you a
design reuse type plane getting different IP third party the IP product, which are AMBA
comprehensive where there is the plenty of IPs coming from different vendors which has
AMBA comprehensive because there are lots of solution with a ARM based and this is the
IP products can be interconnected with a without any issue.
So, it actually h a coming up with a different SoCs with the multiple features and the SoC
vendor also the semiconductor company can differentiate their design from other competitors
by integrating their own IP at a third party IP which are AMBA comprehensive and then follows
AMBA specification or interfacing or connecting the multiple modules within the chip. So,
which sells both the buyer as well as the vendor for a quick market time to market as
well as easy to integrate and then in development is easier and test is easier because all the
features are there. So, this has enabled availability of good
support for the development of AMBA based. It could support in the ecosystem ok that
is very important for any product to be successful in the system in the market. So, good ecosystem
was developed around the AMBA PC . Now, what are the IP re use write a advantage?
IP reuse requires a common standard while supporting a wide variety of SoC. So, there
should be a common standard, but it should not be restricted restrictive if it is restrictive
then too many PC may not be willing to reuse IP.
So, the common standard allowing multiplevariety of wide variety of SoCs supporting this wide
variety of SoCs is the the most successful feature of AMBA . So, with a different power
performance area required. So, SoCs with different requirements see you may be interested in
building a in SoC for a 16 bit microcontroller for a very high very very low power design
low power environment may be a you know aeronautics or may be it is for a small embedded system
ok in the system phase come you know phase maker or something like that ok or it could
be a big router with a powerful you know performance requirement ok a high power performance at
high performance requirement in SoC it could be built.
So, the AMBA specification should be generic enough or either or either a very low end16
bit or even 8 bit controllers as well as 32 bit or 64 bit bit process known systems. So,
and high performance. So, this kind of a this these two are very very wide requirement right,
but AMBA specification needs it so, that is why it is successful.
And AMBA is a coherent hub interface with anotherstandard you know AMBA 5, interface
ARM you know that interface ARM extends performance and scalability to many coherent processors.
So, this is not even restricted to only single processor environment even multiprocessor
environment with chi next level of specification of AMBA helps you in having multiple processor
in the system ok. Cache coherency and then you know multiple processor are its own cache
l 1 and l 2 maybe l 2 cache memory common then there should be cache coherent built
into product. So, those kind of features have to supported.
So, the CHI takes care of that. And multilayer architecture acts as a crossbar
switch between masters and slaves in AMBA 3 system. So, multilayer systems in terms
of area ok when you have that interconnect going over multiple layer the effectives area
occupied with a bus comes down and the width of the bus see it actually this AMBA bus varies
in terms of bit from 8 to 1024 bits ok. The data bus width of the AHB bus could be
nearly in trans 8 bits 1024 bit this is a very very wide support in terms of number
of data lies in the bus. So, if we need to support this without pattern pasting on the
area as well as signal integrating issues, there should be some design kind of multilayer
architectures which will help you in terms of achieving the speed that is required for
making a performance and without sacrificing on the area or the noiseon the bus. So, availability
of the system will be better when you increase the speed of the transaction over the bus.
So, that should be some design elements built into the system. So, that it is also there.
So, the parallel links allow the bandwidth of the interconnect to support the peak bandwidth
of the masters without increasing the frequency of the interconnect. See when you have a multiple
layer then you can increase the data width once the data width is increased then without
increasing the stoke rate ok without increasing the stoke rate that bandwidth can be increased.
Because within one clock cycle ok so, much of data is getting transferred. So, we get
the peak performance peak bandwidth without increasing the frequency of the interconnect
so, that can be achieved. So, AMBA promotes design reuse by defining
common interface standards for SoC modules. So, this is the very important again I am
reiterating that, it is a common interface standard for SoC module ok good.
So, before we get into the some bus titles and their interfaces let us see the what are
theconventions this all of us are cleared and there are there is a grey area, the value
of the bus NH 100 is not defined ok when there is a transient glitch in the bus and the bus
it will be interpreted like this which is expected ok.
And then when a bus from either from highly or low is is becoming a low sorry high becoming
a high this is visible into then bus is shown like this ok particular time in ok these are
all at particular time t. So, the value could be 1 or 0, but it is a stable state ok it
is completely stable it driven properly and highly impedance state; that means, there
is a very important property of supporting a low power design.
Because once the bus is on high high impedance nobody is driving the bus. So,it is not drawing
the current and its capacity expect on the soc and the system is also less . So, high
impedance state is shown like this and any bus in change in the signal is shown by this
particular pin and when it is coming from high impedance to stable state it will be
changing ok for a moment and then impedance stable bus like this ok these are the different
signals. Shaded bus and signal areas are undefined.
The bus or signal can assume any value within the shaded area ok it could be 0 or 1 or it
could be even you know some intermediate values ok not getting anyone, we do not bother about
no module which is connected with bus will bit transmit at this time. So, it it is take
is nothing no other module will go a real anything corrupt corrupted data doing with
that. The actual level is unimportant and does not affect normal operation, that is
what I am trying to say it does not affect a normal operation any objective modules connected
to the bus ok. Let us now see a a overview of the AMBA ok
let us look at some more details about AMBA. So, it was introduced in 1997, AMBA has got
two levels of hierarchy I have already told you this ok ok Advanced High performance Bus
or ASB. So, this is one level ok another one is advanced peripheral bus. So, now,giving
you some more the AMBA is a standard architecture that is the multi microcontroller bus architecture
under that different bus standards are there ok.
So, either AHB or ASB will be in a system and APB will be there, I will give you a demo.
I will show you a diagram where you will understand what is this peripheral bus this is for a
low power low performance ok peripherals to be connected and when a a low performance
bus is connected to a peripherals are connected to a directly they are connected to the high
performance bus, because of the delay in the of the peripherals intersystem the performance
of the high performance bus or the the transactions on this bus by high performing modules like
processors. And memory wont memory is not high performance
that appears you know with a got very good you knowaccess time, no will be delayed because
of the presence of this. So, that is why they divided this; so, low performance and low
power device you know not only low power actually low performance peripheral which are slow
peripherals are do not connected to the high performance bus. That way because of the low
speed peripherals the highly you knowthehigh performance bus and the modules connected
to them almost slow down ok that is the purpose of two levels.
On chip test access that is a very important which I mentioned built in structure for testing
modules connected on the bus. So, this is helps in time to market and a minimum of 32
bit data operation is recommended in the standard and it is extendable to 1024 bits ok. Minimum
of a 32 bit is recommended, but 8 bit also you can provide the 8 bit data bus ok. So,
this is thehigh level overview of AMBA. Now, let us lets I will I will tell you what
all thesome idea around high performance bus ok here ok. So, in this AHB bus sorry ok the
AMBA AHB is a high performance high clock frequency system modules system modules ok
high clock frequency system modules are connected to the bus. AHB acts as a high performance
system backbone bus ok. This is the bus which is used for connecting high performance and
high clock frequency system modules. AHB supports efficient connection of processors,
on chip memory and off chip external memory interfaces. So, the different processors in
the system SoC when I say system is SoC ok because this buses are going to be interface
SoC. So, you know if you have a multiprocessors and this is actually supports multiple masters
in the system. So, AHB supports multiples masters. So, you can have multiple processors
in them and they are all connected to the AHB bus and on chip as well as off chip memories
are connected external memory also connected to the same AHB bus .
With low power peripheral microcell functions. So, this low power peripheral microcell function
also there, but may not be connected directly it could be through APB bridge that I will
talk about later. AHB is also specified to ensure ease of use in an efficient design
flow using synthesis and automated test techniques. So, it also has P wave design slow. So, that
you will be able to integrate the modules different peripherals or differentprocessors
or or memory in the SoC . Now, what is ASB ok? Advanced System Bus the
AMBA ASB is for high performance system modules ok. Actually this is at either AHB will be
there ok in a system high performance bus oris we do not want in a system where this
kind of a high performance is needed because this complexity is more and power consumption
will be more and it meant for a high clock rate peripheralshigh clock rate processor,
but if; that means, the complexity is not needed then designer can chose their ASB there
instead of AHB either this or this right anyone of them.
So, AMBA ASB is an alternative system bus suitable for use where the high performance
features of AHB are not required and ASB also supports efficient connection of processors
on chip memories and off chip. So, whatever AHB supports ASB also supports, but this is
the meant for a low performance systems. So, naturally it will vary or requirement will
be less compared to this comprehensive integer here and power consumption also will be there.
So, this is the designer choice we have to figure out to use AHB or ASB.
What is APB is Advanced Peripheral Bus, AMBA APB is low power peripheral this for low power
peripheral is optimized for minimal power consumption and reduced interface complexity
to support peripheral functions. So, the interface simpler is not complex design and minimum
power consumption. APB can be used in conjunction with either version of AHB or ASB. So, APB
can be this used along with either of this ok. As I told you where processor some memories
will be using these buses; that means, they will be residing on this bus and all low power
peripherals will be on APB. So, they can be APB could be used along with this objects.
A compatible bridge either AHB, APB or ASB, APB module is used for connecting the APB.
So, that is should be a bridge. As I told you a high performance bus cannot be connected
to a low performance bus directly. So, there should be a bridge I will tell you why it
is required and how it helps in satisfying both the requirement ok let us hold on.
Now, before that let me give a get a small overview of what is a macrocell ok .those
who are not from design background we will be able to appreciate this. So, if ASIC is
a chip which is made with custom made for a particular application ok the name fairly
mentioned that application specific is a integrated chip a macrocell array is an approach to the
design and manufacture of ASICs ok its one way of doing ASIC may be not the complete
ASICs may be a part of it. So, essentially it is a small step up from other similar gate
array designs ok Gate array is it will be provided with a different
case ok and then may be more NAND and NOR gate will be there ok and then of course,
some buffers and you know invertors and all that. So, these kind of generic gates will
be provided and then they will be connected according to the circuit requirement you may
realise any circuit using different generic gates or may be a specificNAND and NOR gates
are you know you know then gate, but they will be requires to other gate also to this
you know implement a your final system a circuitry which is the gate array.
Rather than prefabricated array of simple logic gate, the macrocell array ok is prefabricated
array of higher level logic functions; that means, instead of designing you know having
an array ofyou knowsimple logic gate, it is a prefabricated higher level logic which are
they? Flip flops or ALU functions or registers and the like.
So, now because there are registers may be there and then you knowyou knowmay be flip
flops will be there ok. So, this kind of thing may be okor ALU functions ok. So, multiples
may be one not one or two multiple will be this and then how they are connected is what
is decided during the later stages ok. So, so macrocell enables in building such a solution
with a basic functions which are high level value
These logic functions are simply placed at regular predefined positions and manufactured
on a wafer a standard cell library is also sometimes called a macrocell library. So,
they later on they are interconnected to realize the final functionality, that is required
ok this is just its give you a overview of what is the macrocell fine.
Now, typical AMBA based microcontroller before we go into the detail of each of the bus and
how bus transact happen, let me tell you a typical implementation of graph. This is the
one SoC ok which is having both AHB or ASB bus and AHB bus, and it has got a bridge bridge
between a high performance bus and a low power low performance bus.
And what are these devices? They are all devices which has got very very low bandwidth band
you know bandwidth devices. Where the data generated by these devices are all comparatively
very very low rate ok very low rate you can imagine you know how many key key entries
can be generated from a keyboard is basically our ourlimitation on how many keys that we
can press and this may be different you know may be it could go up to kilowatt rate, but
still it is not as big as gigabyte range of transaction that happen over this bus. So,
here they are 2 byte or may be kilobytes of data, get to gigabytes of data transaction
that second of course, ok. So, you can see the difference between these
two and you know almost around t10 power 6 ok. So, let say the bridge is coming in it
let me this is the right time may be I can decide no I can tell you something about what
is the functionality of bridge here. So, both suppose if any of the processor ok
this is the ARM processor and then there is ARM chip ram and then a DMA and external bus
interface memory so, memory external memory connected to this interface. So, this could
be a master and this could become a master and of course, this will be a slave memory
and this will be a slave in the AHB bus or a ASB bus.
Now, this master ok master is one which initiates transaction of the bus and slave response
with the that whatever the master asked for. Now this master could communicate to a peripheral
also. So, you might have written some code or may be a device driver interface with you
know connecting to the UART task now the ARM processor is starting to the peripheral means
or you are trying to write one character into the bus into this particular register which
needs to be UART will be connected to your p c may be ok let us assume this is the PC
is therea TSD RSD ok these aretransmit and receive ok data flows in this way and data
flows here. So, characters will be sent over the serial
bus ok some baud rate may be ninety 9600 baud rate 11 points 11 kilo. So, 96 9600 this is
100 maybe we can say that this is the baud rate. So, every character may be generated
by this processor and then it is writing into the UART.
Now, what happens? UART is a very slow device. So, connecting into that if it waits for UART
to give back acknowledgement it will be unnecessarily holding this bus for long which is meant for
a 2 giga bit of transfer. So, it is not your choice to make this bus wait for some transaction
over with a low performance devices low data rate devices. So, to remove that particular
delay in transact you know in interfacing with the what you know talking to this devices
there is a bridge here. So, which is actually helps in buffering the
data which is coming from either here or in this direction and then completing the remaining
transaction. So, the ARM processor if you wants to write
into the UART, it write into this and then bridge say that ok I will take care of this
a particular UART. So, you can go go ahead with the transaction. So, the transaction
gets completed here and it can communicate with the bus memory or it can caught up to
this or you know it can initiate from DMA with a memory whatever it can do.
So, this bus is speedup for the next transfer while this bridge is helping in terms of completing
the previous transfer that all are neglected. So, that is a job of a bridge ok. So, APB
bridge is always connected to the AHB AHB or ASB through a bridge so, that it does not
in fact, the performance of this bus ok either this. Let you previously let me tell you what
each bus features are high performance of course, pipelined operation what I mean by
pipelined wave when an address transaction happen ok. If the bus transaction actually
you can split it into multiple pin for address and data ok.
Suppose if it is a recycle address will be generated after sometime the data will come
from memory. So, in a pipelined operation well address is generated for the previous
cycle and the data is yet to come, another address generation could happen. Get the transfer
for another transaction that you knowsomething do with a we can overlap the operation that
is basically you know typical to pipeline in the instruction, where one instruction
will be in a fetch stage and another instruction will be in a decode stage and another one
will be in a execute stage, the bus transaction also can be in different stages. So, that
is called pipelined operation. So, because of that the efficiency of the bus is invoked.
So, the bus is not idle at any time waiting for some memory to respond because some other
transaction can be initiated. For example suppose ARM wants to you know
write something into this bus or read from some this memory, it will take some time for
it to respond that to the data. By this time may be DMA can initiate some transaction with
this external bus. So, address can be put here and it will be resolving that address
for it to write something from may beyou know from RAM to you know external RAM or from
some other peripheral here connected that another processor here. So,some other memory
ok a macro memory to or peripheral to memory whatever it is.
So, when multiple transaction happen it could be pipelined so, that is what is the advantage
of the AHB bus ok sorry. So, multiple masters could be there. So, another processor can
be there. So, this could be a master or ARM could be a master or DMA also could be a master
burst transfers are possible; that means, one ASCI question cycle forward by multiple
sequential set spilt transaction is possible multiple transactions can be split and they
can be executed. So, the effective data idling time of your bus is minimized ok that is the
features of AHB. ASB similar thing. So, you see this only these
two are not there in the ASB because it is a complexity is less and is for low performance
devices where you do not want a complexity of ASB then you can go into the ASB ok. Now
what is APB Advance Peripheral Bus which is a low power latched address and control simple
interface and suitable for many peripherals. So, now, you can multiple peripherals can
be connected here ok these are the latched address control very good.
So, now let us go into some more details of AHB. This is the typical bus transfer of AHB
bus. You see here everything is appointed with head to stay which is AHB signal ok and
HCLK is the similar to MCLK we saw ok main clock in the ARM HCLK is for the AHB bus with
the main clock. So, initially it is address phase and then the data phase in the clock.
So, address is putting assume that its a read data ok. So, write data it could be a this
is showing you a write data what what is happening and the read data ok.
And here what you assume is the data width of 32 bits ok it could be as I told you it
could be varies from 8 to 1024 bit. So, in a transaction in a transfer 1024 also bits
also in one transaction, but they recommended is 32 bit
And then what happens is during in address phase address is given ok and then the write
data is available in this data phase when after this HREADY ok by the. So, memory with
with the processor this is coming from processor suppose this is coming from some memory sorry
master, it could be a ARM processor ok it wants to transact over the bus with the memory.
So, slave is the memory correct. So, if you if you wants to write a data into the memory.
So, the memory has to tell whether it is ready to accept the data byHREADY is the positive
value. So, when it becomes high it means that it is ready to accept the data. So, when this
is made high then the data is put. Now, suppose in this clock cycle also if this
remains continuous to be low what will happen that is called wait phase. Because the memory
wants to add more wait phase because it is still yet to decode the address or the memory
is the slow device, it is the low you know performance memory. So, in this case it can
you know it will put some wait case by extending this it will not make it high and then it
will delay the transaction. So, the master ARM has to wait for data available
until this goes high when this goes high in this way ok clock way. Then when it becomes
low the data is made available and the memory can fetch that during this time it it will
take a you know data which is available on the bus and then it will bring down this value.
So, if it happens to be you know sequential access may be it will continue to how hold
it and then it will give you the other data that I will show you later and what about
this? This is for reading the data. So, when it says that I am ready to provide the data,
then the master can read the data from here. So, it is showing the write data from master
to slave this is the reading a data from slave by master ok. So, the data will be available
when the HREADY ready from the slave is made high I hope this is clear to you this particular
transfer. Now, I mention that there is a centralized
arbiter in the bus why is it require? Because multiple masters are supported in the AHB
bus that should be an arbiter. If there is there was only one master in the system then
there is no need for an arbiter. So, this is only what is going to be initiating any
transfer. So, this master is in control of the bus and it does not have to worry if anybody
is using the bus or not. But once there are multiple masters in the bus, then everyone
everyone is to make sure that the bus is free for the master to transact over the bus.
So, to unless otherwise there is somebody who is centralized and come you knowlooking
at transaction happening over the bus, the individual masters may not be aware of what
is going on. So, that is why the centralized arbiter takes care of GB access to the bus
ok. So, it can even associate somesome master
as a default master; that means, if nobody else is asking for the bus the default master
will be given the control of the bus. So, if the default master will be suppose this
is the ARM processor maybe we can make it as a default master that is considerable.
So, if no one else wants the bus, this will be given otherwise there will be a priority
and then accordingly the arbiter decides about who will be have having the control of the
bus at any particular tangent time . So, this kind of what all the you know interfaces
with the arbiter and the master? There is abus requests coming to the arbiter ok requests
coming bus request is coming from the master to the arbiter and the grant going ok grant
going to the particular master. So, how many such lines will be there? With every ok master
there will be a request and grant connection ok one will be in this direction, one will
be in this direction ok request and grant. So, arbiter gets all the request from everybody
every masters in the system and then it which choses one of them based on some priority
ok and then this access to one of the master. So, grant will be only one may be it has chosen
this, then only one master will get the grant and then they when the master will drive the
address or data based on whether it is a right cycle or maybe it is wait for the data if
it is a real cycle. So, this is how the AHB bus ok connected to by different masters communicate
over it with a different place in the system. So, what is the order? Before any master wants
to transact over the bus they need to get the permission from the arbiter which is the
centralized arbiter looking at all the request coming. So, all the masters should be connected
to the arbiter like I just told here and then they will be granted bus at a particular time.
So, what happens? One of them will be based on the choice, one of the address coming from
any one of the master will be going to the bus and then based on a choice again the data
driven by ok data driven by any of the slaves will be going to the particular master ok.
Only one will be driving anyway one of the slave because based on the address one of
the salves will salves will respond and then it will be given to the particular master
and this not takes care of, multiple takes care of, choosing the particular master based
on the grant given by the arbiter . And then what happens the decoder?The data
coming is decoded and then it is given to the particular master ok read data master.
So, this is the this is how the interface is between between the set of slaves and the
set of masters in the AHB bus ok I hope this is clear to you
So, AMBA AHB bus protocol is designed to implement a multi master system unlike bus architecture
designed for PCB based systems, the AMBA AHB bus avoids tristate implementation which avoids
tristate implementation where which is not a PCB based system ok. So, the bus is not
going to be on the PCB, it is going to be on the inside the chip. It employs a central
multiplexer interconnect scheme ok. So, it is not the that other devices need not have
to be in a tristate on the chip because there is a master in the system,
It provides higher performance and lower power than using tristate buffers. So, because of
that performance is better and the low power also interface. Because if it is tristate
you know every device use to drive the bus, it will take some time for charging the busbecause
of capacity website there will be, the time taken for signals to stabilize on the bus
will be longer ok a typical tristate system. Whereas, if it is a much place system everything
is actually connected, but power may be a problem, but the thing is it will be easier
for in terms of occurring the top rate ok performance.
And it is a low power than using the tristate buffer okbecause there is not so, manycharging
or recharging you know disturbing of the buses. So, because of the power this this take a
or buffer power consumed by the buses of the signal over the buses will be minimized the
transactions are does ok. If number of transaction over the bus uh is reduced then thepower consumption
will be less. All bus master assert the address and control
signals indicating the type of transfer each master requires and then central arbiter determines
which master has its address and control signal routed to all the slaves. So, you know arbiter
determines or choses the particular master ok grants the bus for a particular master
then that master controls on their control signal what is the control signal? That is
control signal talks about whether it is read or write whetherwhat is the bit of the transfer
whether its you know half power transfer or full power transfer okor may be a byte transfer.
So, this kind of a different thing can be communicated over the bus.
A central decoder circuit selects the appropriate read data and response acknowledge signal
from the slave that it that is involved in the transactions. So, particular responding
you know data coming from the slave device, that will be connected to the a master who
is grant who is holding the bus. So, may be who has initiated transaction. So, that person
will be that master will get the data coming from the slave. I hope this is clear to you.
Now, data transfer its a pipelined or tenured bus. So, address phase of any transfer can
occur during data phase of previous transfer sorry its overlapping; address and data phases
ok of different transactions are overlapped. This is what is called pipelined or tenured
bus because of this overlap performance of the bus is improved ok.
Now, what is the retry? Suppose one one transaction suppose you know it has got a non sequential
address, first address is non sequential and then remaining addresses are sequential; that
means, one disk transaction is done then next address could be then plus 4 may be you know
based on the peripheral data or whatever a data bus. So, that kind of shown ok.
So, this is the indicating as the what types of transaction is happening non sequential
or sequential ok and then why is it idling now? It is idle signal is generated when the
slave response will be RETRY or it says that HREADY is low; that means, the after this
transaction was completed ok HREADY is low; that means, the peripheral or the slave devices
write that that I am not ready to accept the next transaction.
So, because of that okthere is a retry; that means, the data what was initially given ok
the address and the data what was given is not may be written into the memory properly
may be there was some problem, may be there was a corruption in the data, but whether
may be aparity check would be there, and then may be because of a bridges on the bus that
could be data could be corrupted and in the case that device memory device can initiate
a read write; that means, the same data is again address and data may be put on the bus
for that to be accepted by the slave . So, theI am giving the retry example here
and then burst transfer the you know we can have a multiple transaction for a first non
sequential address. So, different addresses are given now I have to see that ok. And if
you see there is a burst transfer that signal is grant; that means, it is communicated with
the devices that the burst transfer is happening and then a different data for a specific those
addresses are given from the bus ok. So, they are all the you know provided again you see
here it was ready in this state and then it became low and then it becomes continue to
be 5; that means, it is ready to accept the data continuously.
So, because of that becoming low you see this 38 is coming again ok it is kept it for long
and then this data is coming here ok. This address is given this is delay actually and
then because of that you see that this transaction it also taking more cycle, after that the
cycles are one clock only. This is taking two clock cycles because this device or slave
device are send back and not ready to take take that particular transaction because initially
the non sequential cycle takes no time. After that the rest of the accesses will be
slow down you know faster for sequential class cycle then spin circuits will will get more
time and I know it takes more time and then it will selects as become fast later on. So,
it clock occurs in all the data coming later on. So, this is one typical examples of the
signal transaction Iif you know if you are not able to follow this, this for shift for
a while and then understand the sequence because this is very important to understand how the
different signals are helping in terms of transacting over the burst.
Now, what is the split transfer now? What happens is one during one transfer ok a grant
signal is withdrawn ok and then for a slave signal to split and then arbiter changes the
grant ok. Now new master drives the address; that means, once the slaves say that the one
master is communicating and; that means, one master is communicating that one slave ok
may be call it as M 1 and S 1. Now, S 1 says thatyou know slaves signals
are split transaction, I like to have this transaction to the split; that means, this
transaction bus cycle is terminated for a you know intermittently and then during that
time the arbiter could give the burst to another transaction, but even a master and the slave
. So, new master drives the address so, that is why you see that another non sequential
address is happening, in between there is an idle cycle because the arbiter take some
time to grant the particular bus and the master has to drive the bus.
So, this cycle is used for arbiter to chose the another master and then communicate to
the master. So, that the other master there should be something pending ok some grant
you know requested pending so, that the arbiter could give a new master. So, do use the bus
and then it is generating another address this is coming from another different master
and a different control signals and the transaction happens. So, the split transaction is communicated
for breaking your transfer transaction happening and then the arbiter decides and then gives
the control to the bus to some other masters. So, this is one typical example of that.
So, what are the bus width scenario? So, one way to improve bus width without increasing
the frequency of operation is to make the data path of the on chip bus wider. So, this
is possible I told you this; however, it is recommended that the minimum of 32 bits used
or maximum of 2 because even even increasing the bus width to this is a better bit you
know though it improves the performance, there are stability reliability issue might be there.
So, the recommended bits are this 32 and 256. For both read and write transfer the receiving
module must select the data from the correct byte lane on the bus. So, as a when if you
remember you know if the byte transfer is happening may be particular you know odd odd
address or even address, a particular word a byte sorry this is the word ok before allbytes
ok. If suppose it is writing onlythis byte some may be the same value can be driven on
all the buses ok and then I was telling earlier that you know based on the memory which is
there, it could take this value and then internally it can write into the particular location
in the memory. But this actually driving the same data over
the multiple buses actually improve increases the power consumption.
So, in this case in the AHB the correct byte lane on the bus needs to be driven. We do
not have to you know replicate the data on all the byte lane ok. So, the module must
select the data from the correct byte lane. So, in the various any peripheral or a slave
connected to the AHB bus should be capable of getting the byte specifically based on
the address, uh you knowwhich byte lane has to be used for reading the data this slave
device should be aware of and then it should do it accordingly either reading or writing
ok replication of data across all byte lanes is not required ok.
Now, let us sketch upon it will not a small introduction to APB. So, APB has three states
one is idle state and had setup state and enable state ok. So, these are the signals
it will be in idle state where nobody is driving the bus ok no power is learn, and it is all
the devices are not into transacting over the bus and then if anyone wants to drive
on the bus, then if the single setup phase and then based on the multiple transaction
happens then it will be in enableand then setup phase it will go into this.
There is no transfer is there then that you know state of the bus goes to idle state ok.
This is the kind of a state transition and this is the selected particular peripheral
device will be selected if it is one ok and then what will be enabled this transact over
the bus. So, here if you see all the signals are updated with the P; that means, it is
its told that it is the APB bus signal whereas, AHB signals were given which has a prefix.
Now, APB states idle state the default state for the peripheral bus setup. When a transfer
is required the bus moves into the setup state where appropriate the select signal is asserted
only one will be asserted ok. And then the bus only remains in the setup state for one
clock cycle and will always move to the enable state on the next rising edge of the clock.
So, once it is setup it is actually one particulardevice in the APB bus you know peripheral is selected,
then it will be in a setup state afterword it will be in enable state. So, that is peripheral
will be either reading or writing to the bus. So, enable in enable state what happens? The
enable signal P enable is asserted and the address write select signals remain stable
during the transition of from setup to enable. So, either write or select signal will be
active during the time . So, this is the critical transfer transaction
over the APB bus, this is the clock this is actually a low you know its not a frequency
clock. So, address is given ok it is valid here and then the write signal is given, that
is writing into this address with a particular data ok and then a particular peripheral is
decided selected and then enable. So, this is the from idle state it enters ok ok. So,
ok yeah. So, what happens? It is in the idle state
here and then it entersetup state and then enable state. Once it is enabled it is in
enabled state. So, this is the setup state setup this is enable state ok and then this
is the idle state. So, now, we may wonder, why is it address and the write signal continuity
to be this idle where they not driven look. In order to reduce power consumption the address
signal and the write signal will not change after a transfer until next access occurs.
See as I told you when there are not you know signal transitions, then the power consumption
will be consumption will be reduced. So, to keep that and it is not tristated as you remember
this is not tristated bus. So, the peripherals need not be taken off from the bus of the
bus need not be tristated. So, the other signal will remain other whatever
the earlier cycle whatever the address put on the bus will continue to be there on the
bus until the next select is happening and then the next address is put, till then there
will be same address and byte signals will not maintained.
So, that is the read transfer this is the read, that is the write transfer this is the
read transfer. So, the data is comes in late ok . So, the device is selected and then enabled,
and the data is driven by the peripheral device ok master read from the slave read write read
transfer I hope this is clear to you very simple.
So, APB bridge. So, this is the kind of a APB bridge which I have mentioned. So, all
the you know the P P data and the rest all this all connected to this ok and then the
system bus to the system bus either it could be ASB or AHB ok this particular APB bridge
looks like a slave ok. So, that is why the slave interface is connected. So, the ASB
bus or AHB bridge will be on this side connected to this.
So, we are not showing any of the state signals here ok they are all here. So, it is the from
the AHB bus this is one of the slave device and then rest of the signal are all on the
APB bus side. So, APB bridge is the only bus master on the a p AMBA of APB ok. So, AMBA
APB APB bridge is only bus master in addition the APB bridge is also the slave on the higher
level system bus. So, on the APB side the bridge is the master
ok. This this is what is going to actually mimic any transaction happening between the
devices on AHB cycle to APB peripheral. So, actually this is the master as far APB is
concerned sorry APB on the APB bus the APB bridge is the master whereas, on the AHB side
this is the slave. So, this is AHB side okthough the signals are all from APB and this is the
APB side suppose if you take, it begins like a master on this side and begins like a slave
on this side. So, whatever data is coming from AHB is buffered
here and then later on deliver by choosing a particular one of the devices slave devices
and then this is generating these would address would have come from this right.
So, it will based on this address, it will now bridge particular device is selected and
then it drives to same masters here may be modify let me bit if it is recommend and then
your particular peripheral device will be selected and the data whatever given suppose
it has got read ot sorry write, the data is already buffered and the address is also buffered
both will be driven driving here. So, by the time thismaster who was actually originally
driving this, would have gone into completed the transaction and some some other transaction
may be happening on the AHB side. There are this is still going on on the APB side, that
what is the advantage of having a bridge. So, with this we have come to aend of this
session which talked about all the a AMBA architecture, this is the very very high level
overview of this buses ok.I think with this introduction if you can read with based on
your intent or based on what you are trying to design hardware, either as a hardware designer
or as a software embedded software developer. You should be able to read through all the
manuals of learning different buses and understand more details about, how certain things need
to be interfaced ok in a SoC ok. So, I am very happy to share this with you I hope this
was useful to you . And see you in the next lecture may be looking
at one of the peripherals with. So, we will be talking about some peripherals in the next
lecture ok have a nice day. Thank you very much for your attention; bye
bye .

Transcript for:ARM Based Development: Session 32 - AMBA Architecture

Transcript for:
ARM Based Development: Session 32 - AMBA Architecture